SU1443199A1 - Logical phase-difference demodulator - Google Patents

Abstract

The invention can be used to build receivers of digital information transmission systems. The purpose of the invention is to increase the speed of receiving information while increasing the frequency of manipulation. The device contains the shaper 1 of the input signal, r-2 frequency reference, triggers 3, 4 and 5, counter 6, el-7 and 8, el-OR 9, decoder 10 and sequential register 11 "To achieve the goal zl-t OR 12, delay block 13, code converter 14 and parallel register 15 are entered into the device.

Description

The invention relates to communication and can be used in the construction of receivers of digital information transfer systems.

The aim of the invention is to increase the speed of receiving information while increasing the multiplicity of manipulation.

On. Fig. 1 shows a structural electrical circuit of the logical azifferent demodulator for Fig. 2 — types of transmitted signals with a single (Fig. 2a), two fold (Fig. 26) and three-time (Fig. 2c) manipula 1sh; on figs, temporary diagrams, as a matter of law, the work of a demod torus with threefold manipulations.

The logical phase-demodor demodor contains the shaper 1 of the input signal, the generator 2 of the reference frequency, the first 3, the second 4 and the third 5 triggers, the counter B, the first 7 and the second 8 elements AND, the first element 1-ШИ 9, the decoder 10, the sequence register 11, second element OR 12, block 13 delay2 converter code 14 and parallel register 15 „

The logical phase-difference demodulator works as follows;

A digital signal arrives at the input 1 of the input signal, information from several independent sources. The types of digital signals when transmitting information from one, two, and three sources are shown respectively in Figures 2a5 26 and 2. Phase difference control on the forward side is provided by changing the polarity of the signal. at the boundaries of the clock interval Lg by using direct or inverse signals (Fig2) „

In the input signal conditioner 1, the received signal is filtered, amplified, limited, consistent in level with digital elements, and the digital signals generated at its outputs (Fig.) Are input to the clock inputs of the second 4 and third 5 triggers, setting them positive front to zero state The presence of zero potential at least at one of the installation inputs of counter 6 allows the counting of pulses from the generator output 2 reference frequency, tota, frequency f. which is set depending on the required

accuracy of reference of counting pulses to the moment of the beginning of the count. For example, with f 100 - XT-accuracy with

viscous counting pulses to the moment

the start of counting does not exceed one period of the oscillator frequency 2, i.e. no more than one percent of the duration of the clock interval f.

After the counting mode is established by the positive front of the direct or inverse signal from the output of the imager 1, the counting of the reference frequency pulses from the output of the generator 2 by the counter 6 until the moment

 2 () о, where m is the multiplicity of manipulation. At the moment of time

 t a pulse from the output of the decoder 10 sets the triggers 4 and 5 to one. This leads to resetting the counter 6 to the zero state and stopping the counting until

the arrival of the following positive front from the output of the driver to one of the triggers 4 or 5. The interval for stopping the counting is shaded in figs,

The first output of the decoder 10 generates a sequence of narrow pulses (Fig. 3b), delayed relative to the beginning of the period G of the input signal by time t ,. -rffir about

one

On the remaining 2 -1 outputs of the decoder 10, pulses are formed with a delay relative to the adjacent output to

time L –r; 7i ° These pulses

combined in the element OR 12

(FIGOZE), arrive at the clock input of the serial register 11

5 The information input of register 11 receives a signal, which is the result of analyzing the change in the polarity of the input signal during one clock interval.

Q Analysis is carried out by a circuit consisting of trigger 3, the signals at the outputs of which are shown in fig. from the output of the element OR 12 (FIGURE). The result of the recording is presented in the form of zeros and edinits.

(2 - 1) -discharge code from the outputs of register 11 is fed to the inputs of code converter 14. On the m outputs of code converter 14, information signals are sent from m independent information sources. In order to eliminate contests, the signals from the outputs of code converter 14 are written in parallel - alarm register 15 by the signal from the output of block 13 delay. The signals at the outputs of the register 15 (Figs. 3i, k, l) are output information signals of the logical phase difference demodulator.

Claims (1)

Invention Formula A logical phase difference demodulator containing a series-connected input driver, a first trigger, a first element AND and a first element OR, a series-connected reference frequency generator, a counter and a decoder, and a second element And, the second and third triggers, whose outputs are connected to the setup inputs the counter, the input driver input signal is the input of the logical phase difference demodulator, the first output driver input signal is connected to the second input of the first element And the one and to the clock input of the third flip-flop, the second output of the input signal shaper is connected to a first input 0 five five 0 five the Inc element of the clock input of the second trigger, the second code of the first trigger is connected to the second input of the second element I, the output of which is connected to the second input of the first element SH, the first output of the decoder is connected to the clock input of the first trigger, and the second output of the decoder is connected to the installation inputs of the second and third Triggers whose information inputs are grounded, characterized in that, in order to increase the speed of receiving information while increasing the multiplicity of manipulation, a second OR element, a delay unit, and Consistently connected serial register, code converter and parallel register, the outputs of which are the information outputs of the logical phase difference demodulator, the output of the first SHS element is connected to the information input of the serial register, the second output of the decoder is connected to the input of the delay unit, and the first input of the second SHS element whose output connected to the clock input of the serial register, the additional outputs of the decoder are connected to the corresponding inputs of the second element OR-coagulant, and the delay unit output is connected to the clock input of the parallel register and the output clock is a logical phase difference demodulator. , O in / yy 000 p 001 010 d-u- i jii. .. . . , un, ..... / and 11111 ft t 000 a ft 11100 fJoJJJT noooTo 1111110 & iuoit i JFH.ra