SU1374400A1 - Digital frequency discriminator - Google Patents

Abstract

The invention can be used in digital measuring devices and provides increased reliability of operation. The digital frequency discriminator contains two channels consisting of three JK-flip-flops 1,2, 3 (4,5,6), two elements AND 7, 8 (9, 10) and element AND-NOT 11 (12), elements AND -NOT 13, 14, RS-trigger 15 and element And 16. Input signals with periods T, T are received via buses 20, 21. Tires 17, 18, 19 receive clocking sequences of TI 1, TI 3, TI 2, respectively. JK triggers 1, 4 are set to state 1 by a negative differential respectively. input signal. At T T difference pulses. pass to the output bus 23. At T 7 Tj, differential pulses pass to the output bus 24. At 1 t there are no pulses on the output tires 23, 24. 2 Il.

Description

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The invention relates to automatic control devices, can be used in digital measuring devices, and can also work on a calculator during information processing.

The purpose of the invention is to increase the reliability of work.

Figure 1 shows the structural electrical circuit of the proposed digital frequency discriminator; FIG. 2 shows timing diagrams of work that are related to his work.

Digital frequency discriminator 15 contains two channels, each of which contains JK-triggers 1 - 3 (4 - 6), the elements And 7 and 8 (9 and 10) and the element AND NOT 11 (12), the elements AND NOT 13 and 14, RS trigger 15, element 16, 20 input buses 17-19 of three clock sequences TI1, TIZ, TI2, input buses 20 and 21, and reset bus 22.

Digital frequency discriminator works as follows.

In the initial state, the JK triggers 1 - 3 and 4 - 6 of each channel are set to the Zero state. Input signals with periods T and T, for example, (fig.2e), at the output 24, pulse signals are absent in this case (fig.2g).

When a negative differential first arrives at the input bus 20, which sets the JK-flip-flop 1 to one state, and before the second negative pepper arrives at the input bus 20, the denial 1 arrives: there is a differential difference on the input bus 21, which sets the JK-flip-flop 4 in one state, then on all inputs of the NAND 13 element there are 1, at the output of this NAND 13 element - O, which sets the RS-trigger 15 in the single state. The zero output RS-Tprfrrepa 15 goes to the zero state and resets the JK-triggers 1,4,2 and 5 to the zero (initial) state.

When, after the arrival of a negative differential on the input bus 20, the JK flip-flop 1 is set to one. If the negative perapad on the input bus 21 arrived before the arrival of the second negative differential on the input bus 20, then at all inputs of the AND-HE element 13 there are 1,

measures, when T T,, are received by wi-30 and at its output - O, which is set forth by words 20 and 21, respectively (Fig. 2a, b). With the arrival of a negative pulse differential over bus 20, JK-trigger 1 is set to one. If a negative differential does not appear on bus 21 until the second negative differential arrives on bus 20, then with the arrival of the second negative differential across bus 20, trigger 2 is set to a single connection. On the negative edge of the clock pulse TI1 (Fig. 2b), the JK-flip-flop 3 is set to one state. After that on pshna 18

Puts the RS flip-flop 15 into one state, the zero output of the RS flip-flop 15 goes to the zero state and resets the JK triggers 1 and 4 to the zero state. The inverse outputs of JK-flip-flops 1 and 4 have level 1, all inputs of the NAND 14 element contain single signals that bring the output of the NAND 14 element to the zero state and set the RS flip-flop 15 to zero, the initial one, the At the output tires 23 and 24 pulses are missing.

When T 7 T and digital frequency

TIZ clock pulse arrives (fig.2gd5 discriminator is in the original

and through the element AND 7 enters output 23. Then the clock pulse TI2 arrives on the bus 19 and through the elements AND-NOT 11 and the element 8 sets the JK flip-flop 2 to the zero, initial state. According to TI1, the JK flip-flop 3 is set to zero, the initial, state.

Before the arrival of a negative

50

With the arrival of a negative differential on the input bus 21, the JK-Trigger 4 is set to one. If the negative transient across the input bus 20 arrives before the second negative differential travels along the input bus 21, then the JK-trigger 1 is set to one state, the AND-NE element 13 is set

(fig.2e), the output 24 of the pulse signals in this case are absent (fig.2g).

When a negative differential first arrives at the input bus 20, which sets the JK-flip-flop 1 to one state, and before the second negative pepper arrives at the input bus 20, the denial 1 arrives: there is a differential difference on the input bus 21, which sets the JK-flip-flop 4 in one state, then on all inputs of the NAND 13 element there are 1, at the output of this NAND 13 element - O, which sets the RS-trigger 15 in the single state. The zero output RS-Tprfrrepa 15 goes to the zero state and resets the JK-triggers 1,4,2 and 5 to the zero (initial) state.

When, after the arrival of a negative differential on the input bus 20, the JK flip-flop 1 is set to one. If the negative perapad on the input bus 21 arrived before the arrival of the second negative differential on the input bus 20, then at all inputs of the AND-HE element 13 there are 1,

and at its output is O, which sets the RS flip-flop 15 to one state, the zero output of the RS flip-flop 15 goes to the zero state and resets the JK triggers 1 and 4 to the zero state. The inverse outputs of JK-flip-flops 1 and 4 have level 1, all inputs of the NAND 14 element contain single signals that bring the output of the NAND 14 element to the zero state and set the RS flip-flop 15 to zero, the initial one, the At the output tires 23 and 24 pulses are missing.

When T 7 T and digital frequency

the discriminator is in the original

state, with the arrival of a negative differential on the input bus 21, the JK trigger 4 is set to one. If the negative differential across the input bus 20 arrives before the second negative differential arrives at the input bus 21, then the JK flip-flop 1 is set to one state, the AND-HE element 13 is set

yes, on bus 21, all subsequent; not negative to zero state, zero signal

The body drops on the input bus 20 are similarly converted and pass through the element And 7 to the output 23 (Fig. 2e) through the element And 7 to the output 23

from the inverse output of the RS-flip-flop 15 sets the JK-flip-flops 1 and 4 to the zero state, and then through the AND-NOT 14 element the RS-flip-flop 15 is set

from the inverse output of the RS flip-flop 15 sets the JK-flip-flops 1 and 4 to the zero state, and then through the element AND-NO 14 the RS-flip-flop 15 sets

in the initial, zero, state.

Let a negative differential arrive on the input bus 21 and set the JK trigger 1 to one and before the negative differential arrives

 ON the input bus 20 came the second negative differential on the input bus 21.

 The second negative differential across the input bus 21 sets the JK-flip-flop 2 to one state. On the negative edge of the TI1 clock pulse, the JK flip-flop 6 is set to one. After that, the TIZ clock arrives on the input bus 18 and through the AND 9 element goes to the output 24. Then the TI2 clock comes on the input bus 19 and through the I-NE 12 element and the AND 10 element sets the JK trigger 5 to zero, the original, state According to ТИ1 JK-trigger 6 is set to the zero state.

Prior to the arrival of a negative differential on the input bus 20, all subsequent negative differences on the input bus 21 are similarly transformed and pass through the element 9 to the output 24

Thus, if T, Т T, then the differential pulses coming through the input bus 20 pass to the output bus 23, if T T, then the differential pulses coming through the bus 21 pass to the output bus 24, if T, - Tj, then there are no pulses on the output buses 23 and 24.

Claims (1)

Invention Formula A digital frequency discriminator containing two channels, each of which contains the first JK-grigger, whose C input is the channel input, the J and K inputs are the inputs of the logical unit and logical zero signals, the second and third JK triggers, moreover, the direct and inverse outputs of the second JK-trigger are connected to the J- and K-inputs of the third JK-trigger, respectively, C-input ten n 5 five 0 five which is the first clock input of the digital frequency discriminator, and the direct output of the third JK flip-flop is connected to the first input of the first AND-NOT element, the second input of which is the second clock input of the digital frequency discriminator, the first AND input, the first input and output of which The third clock input and the output of the digital frequency discriminator, respectively, as well as the second and third IS-NOT elements, the outputs of which are connected to the inverse S and R inputs of the RS flip-flop, respectively, are first and second inputs of the second The NAND element is connected to the second inputs of the first AND elements and the forward outputs of the first JK triggers of the first and second channels, respectively, the inverse outputs of the first JK triggers of the first and second channels are connected to the first and second inputs of the third AND element, respectively , characterized in that, in order to increase the reliability of operation, a second element AND is inserted into each channel, connected between the R inputs of the first and second JK flip-flops, the second input of the second element AND is connected to the output of the first AND element, and the third element AND, the first input of which is connected to the R input of the third JK flip-flop of each channel and is the input of the reset signal, the second input to the inverse output of the RS flip-flop, and the output to the R input of the first JK flip-flop of each channel, and the third inputs of the second and The third AND-NAND elements are combined and connected to the inverse of the second JK-flip-flop of the first channel, the inverse output of the second JK-flip-flop of the second channel is connected to the combined fourth inputs of the second and third AND-NAND elements, and in each channel the direct and inverse outputs of the first JK flip-flop Connected to the J and K-inputs of the second JK-flip-flop, the C- input of which is connected to the C-input of the first JK-flip-flop, and the direct output of the third JK-flip-flop is connected to the third input of the first element I.