SU1188867A1 - Device for synchronizing pulses - Google Patents

Abstract

A DEVICE FOR SYNCHRONIZATION OF PULSES, containing the first and second 3) triggers, the first and second OR elements and the AND element, the first input of which is connected to the C input of the first 3) trigger and the clock pulse bus, and the second input to the first input of the first the OR element, the second input of the latter is connected to the direct output of the first 0-flip-flop, and the output is connected to the output bus of the device; the entrance of the first D trigger, characterized in that, in order to improve speed and reliability, they introduced the element SH -NE and ZK -trigger, the first vJ-input of which is connected to the D-input of the first D -trigger, R-input of the second Z -trigger and input bus, and the second 3-input - to the inverse output of the first D-flip-flop and the first input of the OR-NOT element, the second input of which is connected to the clock bus, and the output of the OR-NOT element is connected to the second s input of the second element. OR, C-input (L ZK-flip-flop connected to the bus clock pulses, R -input - to the inverse output of the second R-flip-flop, and trick to the second R-in ode O -triggera first and to the first input of the first element Hilti.

Description

The invention relates to a pulse technique, namely to digital synchronization devices.

The aim of the invention is to increase the speed and reliability of the device.

FIG. 1 is a block diagram of a device for synchronization; in fig. 2 - time diagrams of his work.

The device contains the first 1, second 2 triggers and third Z.1 trigger, the first and second elements OR 4 and 5, the element OR NOT 6, the element And 7 input bus 8, bus 9 clock pulses, output bus 10. Bus 9 clock pulses connected to the C inputs of the first and third flip-flops 1 and 3j to the first input of the element I 7 and to the second input of the SH-NE element 6. The input bus 8 is connected to and the input of the first trigger 1, the R-input of the second trigger 2 and to the first G - to the INPUT of the third trigger 3, the second input of the element AND 7 is connected to the first input of the first element OR 4, the second input is the last connected to the direct output of the first trigger 1, and the output to the output bus 10. The output of the element AND 7 through the second element OR 5 is connected to the C input of the second trigger 2, the inverse output of which is connected to the first R-input of the first trigger 1 and with the R input of the third trigger 3. The second 3 input of the third trigger 3 is connected to the inverse of the first trigger 1 and to the first input of the OR-NOT 6 element, the output of which is connected to the second input of the second element OR 5, the output of the third trigger 3 b is engaged with the second R input of the first trigger 1 and with the first input of the first element OR 4.

The device for synchronizing pulses works as follows.

In the initial state, all three triggers are in the zero position. The impulse arriving at the input bus 8 is applied to the D-input of the first trigger 1 and L-the input of the third trigger 3. The closest front of the clock pulse sets to 1 the first or third triggers. Trigger 1 is set if the positive edge of the clock pulse comes first, and trigger 3 - if the negative edge arrives. Let the positive edge of the clock pulse come first. The trigger 1, having been set to 1, blocks the third trigger 3 from the inverse output with a zero level. On the B-NE-6 element, a low level coincides with the inverse output of the first trigger and a low level on the bus 9 clock pulses when the clock pulse ends. The positive front from the output of the element OR NOT 6, having passed through the second element OR 5, cocks the second trigger 2 to 1. The zero level from the inverse output of this trigger sets the first and the third to O: triggers. The forward edge of the synchronized pulse is formed at the forward output of the first trigger 1. This pulse through the first element OR 4 enters the output bus 10 of the device. At the end of the input signal on bus 2, the second trigger is set to O and unlocks the first and third trigger 1 and 3. In case the negative edge of the clock pulse comes first, the third trigger 3 is set to 1 and the first trigger 1 is blocked from the forward output by R input.

The high level from the direct output of the third trigger 3 coincides on the element And 7 with a positive front of the next clock pulse.

The positive front from the output of the element And 7, after passing through the second element OR 5, cocks the second trigger, which, as in the previous case, resets the first and third trigger 1 and 3 to O. The pulse generated at the output of trigger 3 through the element OR 4 enters on the output bus 10 device. At the end of the input pulse, the second trigger 2 is set to O, thereby unlocking the first and third triggers 1 and 3.

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Claims (2)

DEVICE FOR SYNCHRONIZING PULSES, containing the first and second D-flip-flops, the first and second OR elements and the And element, the first input of which is connected to the C. input of the first D-trigger and to the clock bus, and the second input to the first input of the first OR element , the second input of the latter is connected with the direct output of the first D-trigger, and the output is connected to the output bus of the device, the output of the AND element through the second OR element is connected with C-input of the second O-flip-flop, the inverse output of which is connected to the first R-input of the first O-flip-flop, characterized in that, in order to improve performance and reliability, an OR-HE and EC-flip-flop element is introduced into it, the first E-input of which connected to the D-input of the first D-trigger, R-input of the second D-trigger and the input bus, and the second 3-input - to the inverse output of the first D-trigger and the first input of the OR-NOT element, the second input of which is connected to the clock bus, and the output of the OR-NOT element is connected to the second input of the second element. OR, C-input of the JK trigger to the clock bus, R-input - to the inverse output of the second D-trigger, and the output to the second R-input of the first D-trigger and to the first input of the first OR element.