SU1070687A1 - Pulse synchronization device - Google Patents

Abstract

A DEVICE FOR SYNCHRONIZATION OF PULSES, containing an OR element and three triggers, the D and S inputs of the first of which are connected to the common and input buses, respectively, and the output is connected to the O input of the second trigger, the R input of which is connected to the output of the third trigger and one of the inputs of the OR element, the output of which is connected to the output bus, wherein the clock pulse bus is connected to the c inputs of the first and third triggers, characterized in that, in order to improve reliability, the clock bus is connected to the input of the second trigger, output which is connected to another input of the OR element, and T is the input of the third trigger connected to the input bus. e 0 :) 00

Description

The invention relates to a pulsed technique and is intended for use. for use in various types of radio devices, in particular for synchronization of digital devices. A device for synchronizing pulses is known, containing two triggers sequentially connected and an AND element, the output of which is connected to the reset input of the first trigger, the output of which is connected to another input of the And element. The disadvantage of this device is low reliability, since there is a possibility of loss of information when the next input pulse arrives before the process of forming the output pulse from the previous one is completed. The closest to the present invention is a device for synchronizing pulses, which includes an OR element and three triggers, the D and S inputs of the first of which are connected respectively to the common and input channels, and the output is connected to the D input of the second trigger, R is the input which is connected to the output of the third flip-flop and one of the inputs of the OR element, whose output is connected to the output bus, when this clock bus is connected to the C-in input of the first and third C 21 triggers, the disadvantage of the known device is also low reliability, as well If the clock and shifted clock pulses arrive at that moment when a signal is already present on the input bus, the output pulse duration is doubled. The purpose of the invention is to increase the reliability of the device. The goal is achieved in those in the device for synchronizing pulses containing an OR element and three triggers, O and S inputs of the first of which are connected respectively to the common and input buses, and the output is connected to the D input of the second trigger, whose R input is connected to the output of the third trigger and one of the inputs of the OR element, the output of which is connected to the output bus, the clock pulse bus is connected to the C inputs of the first and third triggers, the clock bus is connected to the C input of the second trigger, the output of which is connected toanother input of the element OR, and b is the input of the third three, hera is connected to the input bus. FIG. 1 shows the function of the scheme of the proposed device; in fig. 2 - 4 - temporary diagrammy illustrating his work. o The device contains triggers 1-3, an OR 4 element, a bus of 5 clock pulses, an input bus 6 and an output bus 7. The synchronization inputs of the Triggers are connected to the bus of 5 clock pulses, S is the trigger input 1 and 1 is the trigger 3 input connected to input bus 6. The L input of trigger 1 is connected to the common bus, the output of trigger 1 is connected to the input of trigger 2, the output of which is connected to one of the inputs of the element OR 4. The output of trigger 3 is connected to another input of the element OR 4 and to the input trigger 2. The output of the element OR 4 is connected to the output bus 7 of the device. In the initial state, all the triggers are in the zero state. At the 0-input trigger 1 filed level The device works as follows. Let (Fig. 2) an impulse (Fig. 2a) be received on the input bus 6, the duration of which (tax) is less than the period of clock pulses (TTc), and the positive edge of the clock pulses (Fig. 2c) does not appear during the input signal , and a trigger appears at the output of trigger 1 (Fig. 2c). The first positive edge of the clock pulse received on the Bus 5 clock pulses after the end-of-input signal, this signal is rewritten to trigger 2 (Fig. 2cf), trigger 1 is set: it is reset to zero (Fig. 2c). The signal from the output of trigger 2 through the OR 4 element enters the output bus 7 (Fig. 21). The next positive edge of the clock pulses trigger 2 is also set to the zero state (Fig. 2; :). Thus, on the output bus 7 of the device, it is formed by it. pulse, synchronous clock frequency, the duration of which is equal to the period of clock pulses (Fig. 2f). The trigger 3 at this time remains in the zero state (Fig. 2e) and does not affect the device's ramp. Let (Fig. 3) the input bus 6 receives a signal (Fig. Over), the duration of which (84) is shorter than the period of clock pulses (T-), with the positive edge of clock pulses (Fig. 3 Sv) appearing during the input signal . Then, in the appearance of the input signal at the output of the trigger 1, a signal appears (Fig. 3c). When the positive edge of the clock pulses (Fig. Sv) arrives on bus 5 during the input signal, the trigger 3 is set to one state (Fig. Ze). The signal from the output of the trigger 3 keeps the trigger 2 into the zero-input state (Fig.). From the output of trigger 3 through the element OR 4, the signal enters the output bus 7 of the device. When coming next

the positive edge of the clock pulses of the end of the input signal, since t, triggers 1 and 3, are turned into the zero state (Fig. 3c, Ze). Thus, on the output bus 7 of the device (FIG. 3f) 5, a pulse is formed that is synchronous to a clock frequency whose duration is equal to the period of the clock pulses.

Let (Fig. 4) on the input bus.6 On a signal, the duration of which is greater than the period of clock pulses i. Fig. 4a. The trigger 1 is then set to one (Fig. 4c) l. When a positive front arrives at the same 15 PULTS (Fig. 4c), this signal is also copied to trigger 3. (Fig. 4e), which blocks trigger 2 (Fig. 4d). From the output of trigger 3 through the element OR 4, the signal arrives 20 on the output bus 7 of the device. With the arrival of the following positive clock edges, the signal at the output of trigger 3 (and, therefore, at the device output) is confirmed-25. After the end of the input signal, the first positive edge

Ui

clock pulses trigger 3 is set to the zero state and on the output bus 7 (fig. 4t) the zero level appears. Thus, the output of the device is a formed signal, a synchronous clock frequency, the duration of which

is equal to.

r. t.

TM where ten

the duration of the output signal;

Ттц - period of the clock frequency; o is the number of positive fronts of clock pulses that arrived on bus 5 during the operation of the input signal.

Thus, at the output of the proposed device, a signal is generated that is synchronous to the clock frequency, the duration of which in any case corresponds to the input signal, which causes the high reliability of the proposed device. Besides; the resolution is improved, since the information contained in the duration of the input signal is saved, and the pulse loss is not transmitted.

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Claims (1)

DEVICE FOR SYNCHRONIZING PULSES, containing an OR element and three triggers, the D and S inputs of the first of which are connected to the common and input buses, and the output is connected to the o-input of the second trigger, the R-input of which is connected to the output of the third trigger and one of the inputs of the OR element, the output of which is connected to the output bus, while the clock bus is connected to the e-inputs of the first and third triggers, characterized in that, in order to increase reliability, the clock bus is connected to the s-input of the second trigger, the output of which The first is connected to another input of the OR element, and the input of the third trigger is connected to the input bus. § • 1070687