SU1269245A1 - Device for generating the synchronizing pulses - Google Patents

Description

The invention relates to a pulse technique, and in particular to devices using temporary reference signals, and can be used to control the execution of sequential operations in digital systems.

The aim of the invention is to improve performance by reducing the delay from the start of the trigger signal to the start of the formation of a series of output pulses.

In FIG. 1 shows an electrical schematic diagram of a device; in FIG. 2 - time diagrams of his work.

The device contains a counter 1 pulses, the first 2, second 3 and third 4 synchronous triggers and element And 5, as well as bus 6 trigger signal, bus 7 synchronization pulses, bus 8 setting the initial state and bus 9 output pulses. The R-input of the pulse counter 1 is connected to the initial state setting bus 8, the counter input is connected to the output of the third trigger 4, the zero output is connected to the first input of the And 5 element, the second input of which is connected to the bus 7 of the synchronization pulses and the C-input of the third trigger 4 and the output is connected to the C-input of the second trigger 3. The C-input of the first trigger 2 is connected to the trigger signal bus 6, the R-input is connected to the K-output of the pulse counter 1, and the inverse output is connected to the P-input of the third trigger 4. D-inputs of the first 2 and second 3 triggers and Ι, Κ-inputs' t The third trigger 4 are the inputs of the logical unit signal. Ι,.,., Κ inputs of the counter 1 pulses are the outputs of the device.

A device for generating sync pulses operates as follows.

After turning on the power and receiving the signal to set the initial state on the bus 8 (Fig.2 and 9), the device is in the initial state. At the same time, at the zero output of the counter 1 pulses, on the bus 6 of the trigger signal and the inverse output of the first trigger 2, there is a high potential, at the other outputs of the counter 1 pulses and the inverse outputs of the second 3 and third 4 triggers there is a low potential.

and at the output of element And 5 there is a signal (Fig. 2,6), repeating synchronization pulses on the bus 7 (Fig. 2,8).

After receiving the trigger signal on the bus 6 (Fig. 2,7), the first trigger 2 switches, and a low potential appears on its inverse output (Fig. 2,3), which sets a high potential on the inverse output of the second trigger 3 (Fig. 2) , 4). Thus, the zeroing of the third trigger 4 is removed, and it starts switching at the moments of the recession of the synchronization pulses on the bus 7, forming counting pulses at its output (Fig. 2.5). In this case, on each of the buses 9 of the counter 1 pulses, output pulses are sequentially formed (Fig. 2.10), and there are no pulses at the output of the And 5 element, since a low potential is established at the zero output of the counter 1 of pulses (Fig. 2.1) . With the beginning of the last output pulse, a high potential is established at the inverse output of the first trigger 2, which removes the zeroing of the second trigger 3. Then, with the arrival of the next counting pulse, the pulse counter 1 is set to the initial zero state and forms a high potential at the zero output, which allows the passage of synchronization pulses from bus 7 to the output of element And 5. At the time of the decline of the next synchronization pulse on bus 7 at the inverse output of the second trigger 3, a low potential is set, fixing conductive low potential at the output of the third flip-flop 4 and thereby prohibiting further formation of counts them. The device returns to its original state and is ready for a new start when the potential on the bus 6 of the trigger signal changes from high to low.

The device allows you to expand the functionality by receiving output pulses at the outputs of the counter.

Claims (1)

The invention relates to a pulse technique, namely, devices using time reference signals, and can be used to control the execution of sequential operations in digital systems. The aim of the invention is to improve the speed by reducing the delay from the beginning of the trigger signal to the beginning of the formation of a series of output pulses. FIG. 1 shows the electrical schematic diagram of the device; in fig. 2 - time diagrams of his work. The device contains a pulse counter 1, the first 2, the second 3 and the third 4 synchronous triggers and the element 5, as well as the trigger signal bus 6, the synchronization pulse bus 7, the initial state setting 8, and the output pulse bus 9. The R input of the pulse counter 1 is connected to the initial state setting bus 8, the counting input is connected to the output of the third trigger 4, the zero output is connected to the first input of the And 5 element, the second input of which is connected to the bus 7 of synchronization pulses and the C input of the third trigger 4 and the output is connected to the C-input of the second trigger 3. The C-input of the first trigger 2 is connected to the trigger signal bus 6, the R-input is connected to the K-output of the counter 1 pulses, and the inverse output is connected to the P-input of the third trigger 4. D-inputs of the first 2 and second 3 triggers and 1, K-inputs t The network of its trigger 4 are the inputs of the signal of the logical unit, I ,,,, fK The inputs of the pulse counter 1 are the outputs of the device. The device for forming sync pulses works as follows. After the power is turned on and the signal of the initial state is supplied to the bus 8 (FIGS. 2 and 9), the device is in the initial state. At the same time, at the zero output of the counter 1 imp: ow, on the bus 6 of the trigger signal and the inverse output of the first trigger 2 there is a high potential, the remaining outputs of the counter 1 pulses and the inverse outputs of the second 3 and third 4 triggers have a low potential 52 and at the output of the element I 5 there is a signal (FIG. 2, 6), which repeats synchronization pulses on the bus 7 (FIG. 2, B). After the starting signal (FIG. 2.7) arrives on the bus 6, the first trigger 2 switches, and a low potential appears at its inverse output (FIG. 2.3), setting inverting the output of the second trigger 3, a high potential (Figures 2, 4). Thus, resetting the third trigger 4 is canceled, and it starts switching at the moments of the synchronization pulses falling on the bus 7. At its output, the counting pulses (Fig.2.5) are formed. Moreover, on each of the tires 9 of the pulse counter 1, output pulses are sequentially formed (Fig. 2,10), and there are no pulses at the output of the And 5 element, since a low potential is established at the zero output of the pulse counter 1 (Fig. 2.1) . With the beginning of the last output pulse, the inverse output of the first trigger 2 sets a high potential, removing the zeroing of the second trigger 3. Then, with the arrival of the next counting pulse, the pulse counter 1 sets to the initial zero state and forms a high potential at zero output, which allows the passage of synchronization pulses from tires) 51 7 to the output of element 5. At the moment of the next synchronization pulse falling on bus 7, the inverse output of the second trigger 3 establishes a low potency, fixed uyuschy low potential at the output of the third flip-flop 4 and thereby prohibiting further formation of counts them. The device returns to its original state and is ready for a new start when the potential on bus 6 of the trigger signal changes from high to low. The device allows you to extend the functionality by obtaining output pulses at the counter outputs. Claim device A sync pulse shaping device containing a pulse counter, a first trigger, an And element, a sync pulse bus, a trigger signal bus, the output of the pulse counter connected to the first input of the And element, so that, in order to increase its speed, it has been entered second and third synchronous triggers R-input of the first of which is connected to the inverse output of the first trigger, which is made synchronous, the R-input of which is connected to the K-code of the pulse counter, D-input - with the bus logical one nits, C-input with the trigger signal bus, at3 p. five ... Exodus 54 than the D-INPUT of the second synchronous three1 Gera is connected to the bus of the logical unit, the C-input is connected to the output of the element I, the second input of which is connected to the bus of the clock pulses and the C-input of the third synchronous trigger, P and K-inputs of which are connected to the bus of the logical unit , R-input - with the inverse output of the second synchronous trigger, the R-input of the pulse counter is connected to the installation bus of the initial state, I, ..., whose K-outputs. are the outputs of the device. 6b / j (. 6 pp. eri 2