SU1160479A1 - Multichannel programmed time relay - Google Patents

Abstract

MULTIPLE HEROGRAM-. i JOE TIME RELAY containing frequency divide with counting input and. reset input, p-inlet element, or n control channels, in ka: “the house of which one of the inputs of the I element is connected to the first output of the memory element, and the output of the memory element is to the output bus, which is This is because, in order to expand the functionality by extending the range of time exposures, a decoder is entered into it, the inputs of which are connected to the outputs of the frequency divider and the outputs to the corresponding inputs of the AND elements of the channel, the zeroing bus, and the control bus and two elements OR each for ana moreover, the output of the first element OR of each channel is connected to the first input of the memory element in the same canape, the output of the AND element; It is connected to the first input of the second Element SHS, the output of which is connected to the first input of the first IZH element in the same canape, to the output of the p-input element OR, and to the second input is the memory of the next channel, the output of the p-input element IZH is connected to the reset input the frequency divider, the second inputs of the first elements OR are connected to the zero bus, the second inputs of the second elements OR to the corresponding control buses.

Description

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The invention relates to automatics and can be used in a temporary program control unit.

The purpose of the invention is to expand the functionality by expanding the range to withstand the time of a multi-channel software reLe of time.

The drawing shows a functional diagram of a multichannel software time relay.

Frequency divider 1 with a counting input 2 and a reset input 3 is common to all channels and is performed on m 1.1-1.t binary meters with correspondingly 2.1-2.t m counters and 3.1-3.t m reset inputs. The outputs of the counters are connected to the inputs of the decoder 4 whose outputs, corresponding to the required time delay of each channel, are connected to the inputs n of multi-input elements AND 5.1-5. The respective channels. A direct output n memory elements 6.1-6.P are connected to one of the inputs of the multi-input elements AND of each channel, and the outputs of the AND elements are connected to the input n of the two-input elements OR 7.1-7.p, the second input of which is connected to the pins 8.1-8 Controls where external control signals can be supplied. One input of the second p dvukhvrdovyh elements OR 9.1-9. P of each channel is connected to the nullification bus 10, and the second input is connected to the input of the p-input. of the element OR 11, with n outputs 12.1-12.h of the elements OR 7.1-7.p of its channel and with the output of n memory elements 6.1-6.p of the next channel. Cyclic timer operation is provided by connecting: 12. An output to the input of the element, 6.1 memory. The inverse outputs of the memory elements are connected to each other.

13.1-13.p.

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The time relay works as follows.

The reset pulse pulse through the bus Z is zeroed and the elements 9.1-9. The elements 6.1-6. Of the memory are reset. In the initial state, the logical zero level appears at the direct output of the memory elements, therefore, at the outputs of the multi-input elements AND 5.1-5.P and high 604792

The 12.1-12 moves. The logical zero level also appears. In addition, the output of the element OR 11 will also be a logical zero level,

J therefore, when connected to the counting input 2 of the generator, the time of the driving clock pulses is binary counters p; they operate in the counting mode. In this state, the time relay

0 is arbitrarily long. Its launch can be started from any channel. For example, if a start pulse is applied to the bus 8.1, a control signal appears on run 12.1, while

5, a memory element 6.2 is included, and at its direct output, input and input of the AND 5.2 element, a logic unit level appears. Simultaneously, the pulse from output 12.1 through the element

0 or 11 resets all counters

l.l-l.m to zero state. From this moment, the delay time countdown of the second channel begins. This time is determined by which outputs of the de5 encoder 4 are connected to the inputs of the And 5.2 element. At the time of the occurrence of the level of logical unity 1 on all inputs of the element And 5.2, the output of the second channel 12.2 appears as follows. The same level of the logical unit that resets binary counters to zero through the element OR 11 resets the element through the element OR 9.2. 6.2 memory is reset and includes a memory element of the third channel. The formation of the time delay of the third and subsequent channels occurs as described. The signal from the output 12.n of the last channel turns on the memory element 6.1 of the first channel and starts the next cycle of the time relay operation.

The signals at the outputs of 12.1-12. P have the form of short pulses with time intervals between them, equal to the time delay of the corresponding channels. The output signals on buses 13.1-13.p have the form of rectangular pulses with a duration equal to the time delay of the corresponding channel. .

Interrupting the operation of the time relay can be performed either by applying a reset pulse to the bus 10 null5 or by applying a constant

the level of the logical unit at the reset inputs of binary counters. In this case, after turning off the signal

resetting the program continues from the channel on which the interrupt occurs. If an external control signal in the form of a short pulse is applied to the zero-zero bus 10, and then with a delay equal to the duration of the pulse to the free bus 8 of any channel, you can interrupt the program and advance it from the channel on which bus 8 has a control signal .

Use in the proposed nporpafft HOM time relay one de 1604794

The frequency module, which sequentially after resetting to zero sets the shutter speeds of each channel, allows, compared to the known devices, 5 to extend the functionality of the time relay, practically to get any required time delays. If the decoder outputs are connected to the inputs of the And 5 "1 10 element through switches, then any time delay can be set with any desired accuracy between the start signals and the start of the program.

Claims (1)

MULTI-CHANNEL PROGRAM - i ANOTHER TIME RELAY, containing a frequency divider with a counting input and a reset input, n is an OR input element, η control channels, in each of which one of the inputs of the And element is connected to the first output of the memory element, and the second output of the memory element to the output bus, it is important that, in order to expand functionality by expanding the range of time delays, a decoder is introduced into it, the inputs of which are connected to the outputs of the frequency divider, and the outputs to the corresponding inputs elements and ka of each channel, the zeroing bus, as well as the control bus, etc., there are two OR elements in each channel, the output of the first OR element of each channel being connected to the first input of the memory element in the same channel, the output of the AND element; connected to the first input of the second ^ OR element, the output of which is connected to the first input of the first OR element in the same channel, to the output of the η-input OR element and to the second input of the memory element of the next channel, the output of the η-input OR element is connected to the reset input ^ frequency divider, the second inputs of the first OR elements are connected to the zeroing bus, the second inputs of the second OR elements are connected to the corresponding control buses. > 160479