SU1511850A1 - Device for extracting single pulse from continuous pulse sequence - Google Patents

Abstract

The invention relates to a pulse technique and can be used in computing and measuring devices, in communication systems, automation and telemechanics. The purpose of the invention is to improve the noise immunity by eliminating chatter on the leading edge. The device comprises an input information conversion unit 2, an edge extraction unit 3, triggers 4, 5, a pulse counter 7. The introduction of the trigger 11 made it possible to increase the reliability of the operation and restore the form of the control signal in case of its distortion both on the leading and trailing edges. 6 Il.

Description

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The invention relates to a pulse technique and can be used in computing and measuring devices, 3 communication systems, automation and telemechanics.

The purpose of the invention is to increase the noise immunity by eliminating bounce on the leading edge.

Fig. 1 shows an electrical functional diagram of a device for extracting a single pulse from a continuous pulse sequence; 1big.2 shows the time diagrams of his work; Fig. 3 is an electrical functional block edge selection circuit, an exemplary embodiment; FIG. A shows timing diagrams explaining the operation of the edge selection block; Fig. 5 illustrates the electrical functional diagram of the input information conversion unit, an exemplary embodiment; Figure 6 shows the time diagrams of the operation of the block for the conversion of input information.

A device for separating a single pulse from a continuous pulse sequence contains (FIG. 1) input bus 1, input information conversion unit 2, edge detection unit 3, first and second triggers 4 and 5, OR element 6, pulse counter 7, start bus 8 installations, the first and second output buses 9 and 10, and the third additional trigger 11.

Bus 1 is connected to the input of block 2, the first output of which is connected to the information input of block 3. The second output of block 2 is connected to the synchronizing input of block 3 and to the counting input of the counter 7 pulses. The third output of block 2 is connected to the R-BXO trigger house 4. The first output of block 3 is connected to the R-input of the trigger 11 and the S-input of the trigger 4, the output of which is connected to the second output bus 10 of the device — a single pulse. The second output of the block 3 is connected to the R input of the trigger 5,

the output of which is connected to the installation inputs of the counter 7 and unit 3. The output of the counter 7 is connected to one of the inputs of the OR element 6, the other input of which is connected to the bus 8 of the initial installation. The third output of block 3 is connected to the output bus 9 of the low-frequency signal of the restored form. The output of the element OR 6 is connected With

S-inputs of the trigger 5 and the trigger 11, the output of which is connected to the additional installation inputs of the counter 7 and block 3.

Block 3 selection of fronts .3) consists of the first and second D-flip-flops 12 and 13, the first and second elements AND-HEN 14 and 15 and the inverter 16. At the same time, the information input is connected to the first input of the first HAND element 14 and through the inverter 16. from the D-BXO- House of the first D-flip-flop 12, the output of which is connected to the D-input of the second D-flush 13, to the third output of the block 3 and to the second input of the second element AND-NOT 15, the first input of which is connected with the D-output of the second D-flip-flop 13, and the output with the first output of block 3. The synchronizing input of block 3 is connected to the C-inputs of the first and second D-three 12 and 13. The installation input is connected to the R input of the first D flip-flop 12. The output of the second D flip-flop 13 is connected to the second input of the first AND 14 element, the output of which is connected to the second output of block 3, the Additional installation input is connected. with the S-input of the first D-flip-flop 12 and with the third input of the first element AND-NOT 14.

The input information conversion unit 2 (FIG. 5) contains a pulse counter 17 and an AND-NOT element 18 connected to its outputs. The input of the counter 17 is connected to the input of the block 2, the outputs of the low and high bits of the counter 17 are connected respectively to the outputs of the first regular post-clock -. . of activity (FIG. 66) and the random explorer (FIG. bg). The output element AND-NOT 18 is connected to the output of the second regular sequence (fig.bv),

Upon admission to the input counter. 17 of the pulse sequence (Fig. B), signals of the required duration and period are formed at its outputs.

The device works as follows.

The bus 8 sets the initial state through the element OR 6: (fig. 2z) to the S input of trigger 5 and S is the input of additional trigger 11 and sets them to normal status.

Counter 7 is in the reset state, and block 3 is ready to receive and

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processing information. The condition of the other elements does not affect the operation of the device.

The signals from the input bus 1 (fig. 2a) are fed to the input of the input information conversion unit 2 and form in it signals of a random (fig.2g) and two regular sequences of pulses (fig.2b, c). A pulse of a random sequence of negative polarity arrives at the information input of the edge extraction unit 3, which, on the leading edge of the signals arriving at its sync-lowering input (FIG. 26), produces a positive polarity pulse at the third output (FIG. 2e) and a pulse negative polarity at the first output (Fig. 2e), by which the trigger D is set to one, and a positive field impulse (Fig. 2L) begins to form on the output extraction spike 10 of the single pulse. An additional trigger 11 (Fig. 2m) is set to the zero state, removing the ban on

counter 7. Due to the long links, the signal at the information input of block 3 (FIG. 2d) may be distorted along the leading edge. However, since the trigger 11 is in the zero state, block 3 at this time is under installation in I and the effect of the distorted pulse is not predicted on the formation of the output pulse on bus 9 (FIG. 2e). The next sync pulse arriving at the sync input of unit 3 ends with the formation of a negative polarity pulse at its first output, and the counter 7 produces a negative polarity pulse (Fig. 2k), which through the element OR 6 enters the S input of the trigger 11 and puts it into a single state (Fig; 2 m), the counter 7 is set to the reset state. Upon arrival from the third output of the block 2 of the pulse of the regular sequence (Fig. 2b) to the R input of the trigger 4, it switches to the zero state and on the bus 10 ends the formation of a pulse of positive polarity.

On the falling edge of the negative polarity impulse arriving at the information input of block 3 (FIG. 2d), at its second output expr

a negative polarity pulse (Fig. 2g), which causes the trigger 5 to the zero state (Fig. 2i), is being bathed. Due to the long lines of communication, the signal at the information input of block 3 (Fig. 2d) may be distorted on the falling edge. However, since the trigger 5 is in the zero state, then block 3 in

this time is under reset and the effect of the distorted pulse does not affect the formation of the output pulse on gaine 9 (Fig. 2e).

When switching trigger 5 in

the zero state is removed from the prohibition of counter 7; the counter counts the time during which the pulse distortion stops at the information input of the block 3. During this

time, since block 3 is under reset, a pulse is not generated at its first output and on bus 9. the output signal is not distorted. Next, at the output of the counter 7, a negative polarity pulse is generated (Fig. 2k), which through the OR element 6 enters the S input of the trigger 5 and translates it into a single state (Fig. 2i). The device is prepared for

next work cycle.

Block 3 selection of the fronts works as follows.

The negative polarity signal at the information input (FIG. DB) through the inverter 16 (FIG. DV) is supplied

to the information input of the first D-flip-flop 12, which, on the rising edge of the sync signal from the sync input (Fig. 4a), goes to a single state (Fig. 4d), and since the inverse output of the second D-flip-flop 13 (Fig. 4e) is in the unit state,, then at the output of the element AND-NOT 15 (Fig. 4j, a pulse is formed

negative polarity, which is fed to the first output of block 3. According to the following sync pulse, the D-flip-flop 13 (fig.4d) goes to one, the rest, on the AND-NO element 15 x

(Fig. 4g) the formation of a negative polarity pulse is completed.

Due to the distortion of the pulse at the information input on the leading edge (Fig.4b) at the output of the inverter 16

(Fig. 4b), false pulse may form. However, the trigger 12 does not accept it, since it is blocked by the S input (Fig. 4k). As a result

undistorted pulse from the output of the trigger 12 is fed to the output of block 3 (figd).

ilo to the falling edge of the pulse arriving at the information input, and when it goes into one state at the output of the NAND element 14, a negative polarity pulse is generated, which enters the n4 second output

block 3 (fig.Az).

A negative polarity impulse arrives at the setup input, setting the trigger 12 (Fig. 4d) to the zero state. On sync pulse from the sync bus (Fig. 4a), the trigger 13 goes to the zero state (Fig. 4e) and at the output of the AND-NE element 14 (Fig. 4z) I ends forming a negative polarity pulse. Due to the distortion of the pulse at the information input on the falling edge (Fig. 46), a spurious pulse can be generated at the output of the inverter 16 (Fig. 4b). However, the trigger 12 does not perceive it, since it is blocked on the R input. As a result, a non-: distorted pulse from the output of trigger 12 is fed to the output of block 3.

After the termination of the negative polarity pulse at the unit inlet (Fig. 4i), unit 3 is prepared for the next cycle of operation.

Formula and inventions

1. A device for separating a single pulse from a continuous pulse sequence containing a conversion unit, the input of which is connected to the input bus, the first output — to the information input of the block, the edge highlighting, the second output — with the counting inputs of the front selection block and the pulse counter the third output with the R-input of the first trigger, the S-input of which is connected to the first output of the edge detection unit, the second output of which is connected to the R-input of the second trigger,

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The S-input of which is connected to the output of the OR element, the first input of which is connected to the installation bus to its initial state, the second input to the output of a pulse counter, the installation input of which is connected to the output of the second trigger and the installation input of the edge-selection block, the third output of which is connected with the first output bus, and the second output bus is connected. with the output of the first trigger, which is different from the fact that, in order to avoid noise immunity, a third trigger has been introduced, the R input of which is connected to the first output of the unit; fronts, S-input - with the output of the OR gate, the output - with additional input pulse counter mounting and fronts isolation unit.

2. The device according to claim 1, about tl and - that the block selection of the fronts contains the first and second D-flip-flops, the D-input of the first of which is connected via an inverter with the information input of the block selection of the fronts and the first input of the first element IS-NOT, the second input of which is connected to the direct output of the second D-Tpir -ger, the inverse output of which is connected to the first input of the second element, the output of which is connected to the first output of the frontal separation unit, the second input to the p-input of the second trigger and direct output of the first D-TjMrrepa, with the C input of which It is connected with the C input of the second D-flip-flop and the synchronization input of the edge selection block, the setup input of which is connected to the R input of a new D-flip-flop, the S input of which is connected to the auxiliary input of the front edge block and the third input of the first element I the GNE, the output of which is connected to the second output of the edge separation unit, the third output of which is connected to the second input of the second NAND element.

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Claims (2)

Formulas a. input 1. A device for extracting a single pulse from a continuous pulse sequence, comprising a conversion unit, the input of which is connected to the input bus, the first output - with the information input of the block _; edge selection, the second output with the counting inputs of the edge allocation unit and the pulse counter, the third output with the R-input of the first trigger, the S-input of which is connected to the first output of the edge selection unit, the second output of which is connected to the R-input of the second trigger, The S-input of which is connected to the output of the OR element, the first input of which is connected to the installation bus in the initial state, the second input with the output of the pulse counter, the installation input of which is connected to the output of the second trigger and to the installation input of the edge selection unit, the third output of which is connected to the first 'output bus, and the second output bus is connected. With the output of the first trigger, characterized in that, in order to increase noise immunity, a third trigger is introduced into it, the R-input of which is connected to the first output of the FR ntov, S-input · output -'s OR gate, the output - with additional input of the pulse counter mounting and fronts allocation block. 2. The device according to claim 1, wherein the edge allocation unit comprises first and second D-flip-flops, the D-input of the first of which is connected via an inverter to the information input of the edge allocation unit and to the first input of the first AND element - NOT, the second input of which is connected to the direct output of the second D-trigger, the inverse output of which is connected to the first input of the second AND-NOT element, the output of which is connected to the first output of the edge selection unit, the second input - with the D-input of the second trigger and with direct the output of the first D-trigger, whose s-input is din with the C-input of the second D-trigger and the synchronizing input of the edge selection unit, the installation input of which is connected to the R-input of the first D-trigger, the S-input of which is connected to the additional installation input of the edge selection blog and the third input of the first AND element NOT, the output of which is connected to the second output of the edge allocation unit, the third output of which ·? The horn is connected to the second input of the second NAND element. _g 1111111111II III llllll lllllllll II Illi null I UH ihiiil _δ lppgitgigpl ^^ tpue.3 ₀ gttztlppgshgitppppzzllllpgtllllg in _ΓΊ_Ι ------- ---- 1 — ΓΊ _____ Mr. J l 9— ^{J e} ________________: __________ i -------------------------------- w -jj s - 1_G Fig. Ts a mpllshshlplepplesh ^ ί ТШЬШЬ1ЛЛЛ7Л7ЬГШЛТиТГ1 ί J Ί_Ι LJ ~ 1 — ΓLΓ Ί G ---- 1 G ~ L ² Ί - fie.b