RU2738963C1 - Asynchronous input device - Google Patents

Abstract

FIELD: data processing.SUBSTANCE: invention relates to digital engineering in the field of information exchange using serial asynchronous interfaces. Asynchronous input device comprises input, synchronizing and output buses, shift register, flip-flop and 2AND-NOT element. Distinctive feature consists in fact that additionally introduced are: additional element 2AND-NOT, first, second and third inverters, element 2AND, counter for subtraction, first, second, third, fourth and fifth D flip-flops and resetting bus.EFFECT: higher stability of duration of input signals in asynchronous devices.1 cl, 2 dwg

Description

The invention relates to digital technology in the field of information exchange and can be used in space, aviation, shipbuilding and other industries in serial asynchronous interfaces.

Known redundant device for synchronizing signals (USSR AS No. 378830), containing in each of the trigger channels for recording, storing and outputting information, a majority element and a clock bus.

The disadvantage of this device is the possibility of forming false output signals by its circuit when asynchronous information arrives at the inputs.

In asynchronous devices, input signals can change their duration due to an arbitrary arrangement of sync signals. Moreover, the change in duration can increase or decrease by the period of the sync signals. In the level distributor by A.S. USSR No. 1172002, containing a shift register, the outputs of which are output buses, a synchronization bus, which is connected to the C-input of the main shift register, a clock bus, an additional shift register, an AND-NOT element, an RS-flip-flop, the output of which is connected to the D-input an additional shift register, the output of the first bit of which is connected to the D-input of the main shift register, and the inverse output of the last bit - to the first input of the AND-NOT element and the R-input of the RS-flip-flop, the S-input of which is connected to the output of the AND-NOT element, the second input of which is connected to the clock bus, and the C-input of the additional shift register is connected to the synchronization bus. In this device, the duration does not change and is equal to the number of register bits multiplied by the sync signal period.

The disadvantage of this device is that it is efficient for periodic signals of the same duration. When changing the duration on the input bus or on two buses, i.e. in asynchronous interfaces, the device is not functional. In addition, when receiving information via asynchronous high-frequency interfaces, a problem arises in changing the duration due to the difference in turn-on and turn-off delays on galvanic isolation, cable network, and integrated circuits.

The objective of the present invention is to improve the stability of the duration in asynchronous devices, including serial asynchronous interfaces.

The problem is solved by the fact that an asynchronous input device is proposed that contains input, output and synchronization buses, a shift register, a flip-flop and a 2I-NOT element. Additionally, an additional element 2I-NOT, the first, second and third inverters, an element 2I, a subtraction counter, the first, second, third, fourth and fifth D-triggers and a reset bus are introduced into it.

FIG. 1 shows a block diagram of the proposed device,

Where:

1.1, 1.2 - the first and second input buses,

2 - additional element 2I-NOT,

3 - the first inverter,

4 - synchronizing bus,

5 - reset bus

6 - trigger,

7 - shift register,

8 - second D-trigger,

9 - third D-trigger,

10 - the first D-trigger,

11 - fourth D-trigger,

12 - fifth D-trigger,

13 - element 2I,

14 - element 2I-NOT,

15 - counter for subtraction,

16 - second inverter,

17 - third inverter,

18.1, 18.2 - the first and second output buses.

The first input bus (1.1) is connected to the first input of the additional element 2I-NOT (2) and to the D-input of the second flip-flop (8), and the second input bus (1.2) is connected to the second input of the additional element 2I-NOT (2) and with D-input of the third D-flip-flop (9). The output of the additional element 2I-NOT (2) is connected to the D-input of the shift register (7) and through the first inverter (3) to the S-input of the trigger (6). The reset bus (5) is connected to the reset inputs of the flip-flop (6), shift register (7), the first-fifth D-flip-flops (8-12) and the first input of the 2I-NOT element (14), the output of which is connected to the counter reset input to subtraction (15). The D-input of the flip-flop (6) is connected to a common point, and the output is connected to the D-input of the first flip-flop (10) and with the second input of the 2I-NOT element (14). The sync bus (4) is connected to the sync input of the first flip-flop (10) and the first input of the 2I element (13). The output of the first trigger (10) is connected to the second input of the element 2I (13), the output of which is connected to the counting input of the subtraction counter (15), the least significant bit of which is connected to the sync inputs of the second (8) and third (9) D-flip-flops and to the input the second inverter (16), the output of which is connected to the sync inputs of the fourth (11) and fifth (12) D-flip-flops, the output of the most significant bit of the counter for subtraction (15) through the third inverter (17) is connected to the sync input of the shift register (7), the inverse output which is connected to the trigger input (6). The outputs of the second (8) and third (9) D-flip-flops are connected, respectively, with the D-inputs of the fourth (11) and fifth (12) D-flip-flops, the inverse outputs of which are connected, respectively, with the first and second output buses (18.1), (18.2) ...

FIG. 2 shows timing diagrams explaining the principle of operation of the proposed device.

The device works as follows.

In the initial state, on the reset bus (5), all triggers and the counter for subtraction are set to zero. Upon arrival of the first pulse (zero state) along the first input bus (1.1) at the output of the additional element 2I-NOT (2) (timing diagram 15, a single state is set, at the output of the first inverter (3) - zero (timing diagram 16) and at the output flip-flop (6) (timing diagram 17) - unitary Further, on the edge of the synchronizing bus (4) (timing diagram 18) at the output of the first D-flip-flop (10) (timing diagram 19), a unit state is set and at the output of element 2I ( 13) (timing diagram 20), a pulse appears, which sets all counter bits for subtraction (15) (timing diagrams 21.1, 21.2, 21.3) to a single state, and zero is set at the outputs of the second (16) and third (17) inverters state (timing diagrams 21.4, 21.5).

Since at the input of the third D-flip-flop (9) there was a single state, then at the output along the edge of the signal from the counter for subtraction (15), the third D-flip-flop goes into a single state (timing diagram 23).

The state of the second D-flip-flop (8) (timing diagram 22) remains unchanged.

Further, according to the sync pulses from the counter for subtraction (15) (timing diagram 21.2), the second (8) and third (9) D-flip-flops change their state, which arrives at their D-inputs (timing diagrams 22, 23), and the fourth ( 11) and the fifth (12) D-flip-flops repeat the state of the second and third D-flip-flops (timing diagrams 24, 25) according to sync pulses from the output of the second inverter (16) (timing diagram 21.4). According to the first sync pulse from the third inverter (17) (timing diagram 21.5), the first bit of the register (7) goes into the single state, and then the inverse output of the second bit goes to the zero state (timing diagrams 26.1, 26.2).

When the pulses stop on the first and second input buses (1.1), (1.2) (single state), the zero state is set at the output of the additional element 2I-NOT (2). Since a single state is established at the inputs of the second (8) and third (9) D-flip-flops, a single state is established at their outputs. At the inverse outputs of the fourth (11) and fifth (12) D-flip-flops and on the first and second output buses (18.1), (18.2), a single state is set by sync pulses from the second inverter, i.e. signal production stops.

After the zero state is established at the output of the additional element 2I-NOT (2), then the zero state is set at the output of the first bit of the register (7) (timing diagram 26.1) by the sync pulse from the third inverter (17), and then at the inverse output of the second discharge is set to a single state (timing diagram 26.2). Since the information input of the flip-flop (6) is connected to a common point, the flip-flop (6) is set to zero on the edge from the inverse output of the register (7). Element 2I-NOT (14) goes into a single state, the counter is reset to subtraction (15). The first D-flip-flop (10) on the front from the synchronizing bus (4) goes into a single state. At the output of element 2I (13), the generation of pulses stops. The device switches to the initial state and waits for the next input pulses.

Thus, an asynchronous input device is proposed, which contains the first input, synchronization and the first output buses, a shift register, a flip-flop and a 2I-NOT element. Additionally, an additional element 2I-NOT, the first, second and third inverters, an element 2I, a subtraction counter, the first, second, third, fourth and fifth D-triggers, the second input bus, the second output bus and the reset bus are introduced into it. The first input bus is connected to the first input of the additional element 2I-NOT and to the D-input of the second flip-flop, and the second input bus is connected to the second input of the additional element 2I-NOT and to the D-input of the third D-flip-flop. The output of the additional element 2I-NOT is connected to the D-input of the shift register and through the first inverter with the S-input of the trigger. The reset bus is connected to the reset inputs of the flip-flop, shift register, first - fifth D-flip-flops and the first input of the 2I-NOT element, the output of which is connected to the counter reset input for subtraction. The D-input of the flip-flop is connected to a common point, and the output is connected to the D-input of the first flip-flop and to the second input of the 2I-NOT element. The sync bus is connected to the sync input of the first flip-flop and the first input of the 2I element. The output of the first flip-flop is connected to the second input of the element 2I, the output of which is connected to the counting input of the counter for subtraction, the least significant bit of which is connected to the sync inputs of the second and third D-flip-flops and to the input of the second inverter, the output of which is connected to the sync inputs of the fourth and fifth D-flip-flops, the output of the high-order bit of the counter for subtraction through the third inverter is connected to the sync input of the shift register, the inverse output of which is connected to the sync input of the trigger. The outputs of the second and third D-flip-flops are connected, respectively, with the D-inputs of the fourth and fifth D-flip-flops, the inverse outputs of which are connected respectively to the first and second output buses.

The technical result of the proposed device is to increase the stability of the duration of input signals in asynchronous devices.

Claims (1)

An asynchronous input device containing the first input, synchronizing and first output buses, a shift register, a flip-flop and a 2I-NOT element, characterized in that an additional 2I-NOT element, the first, second and third inverters, an 2I element, a counter on subtraction, the first, second, third, fourth and fifth D-flip-flops, the second input bus, the second output bus and the reset bus, the first input bus being connected to the first input of the additional 2I-NOT element and to the D-input of the second trigger, and the second input the bus is connected to the second input of the additional element 2I-NOT and to the D-input of the third D-flip-flop, the output of the additional element 2I-NOT is connected to the D-input of the shift register and through the first inverter to the S-input of the trigger, the reset bus is connected to the reset inputs of the flip-flop , shift register, the first - fifth D-flip-flops and the first input of the 2I-NOT element, the output of which is connected to the counter reset input for subtraction, the D-input of the trigger is connected to a common point, and the output is connected to D-in by the course of the first trigger and with the second input of the 2I-NOT element, the synchronizing bus is connected to the sync input of the first trigger and the first input of the 2I element, the output of the first trigger is connected to the second input of the 2I element, the output of which is connected to the counting input of the subtraction counter, the least significant bit of which is connected to sync inputs of the second and third D-flip-flops and with the input of the second inverter, the output of which is connected to the sync inputs of the fourth and fifth D-flip-flops, the output of the high-order bit of the counter for subtraction through the third inverter is connected to the sync input of the shift register, the inverse output of which is connected to the sync input of the trigger, the outputs of the second and the third D-flip-flops are connected respectively to the D-inputs of the fourth and fifth D-flip-flops, the inverse outputs of which are connected respectively to the first and second output buses.

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