RU2785272C1 - Asynchronous input device - Google Patents

Abstract

FIELD: digital technology.

SUBSTANCE: invention relates to digital technology in the field of information exchange and can be used in the space, aviation, shipbuilding and other industries. The asynchronous input device contains input, synchronizing and output buses, shift register. The distinctive feature is that in addition the following are introduced: D-trigger, elements 2OR, 2AND.

EFFECT: increasing the stability of the duration of output signals with different durations of input signals in asynchronous devices.

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Description

The invention relates to digital technology in the field of information exchange and can be used in space, aviation, shipbuilding and other industries in serial asynchronous interfaces.

A redundant device for synchronizing signals (AS USSR No. 378830) is known, containing in each of the trigger channels for recording, storing and issuing information, a majority element and a clock pulse bus.

The disadvantage of this device is the possibility of its circuit generating false output signals when asynchronous information is received at the inputs.

In asynchronous devices, input signals can change their duration due to the arbitrary arrangement of clock signals. Moreover, the change in duration can increase or decrease by the period of the clock signals. In the level distributor according to a.s. USSR No. 1172002, containing a shift register, the outputs of which are output buses, a synchronization bus that is connected to the clock input of the main shift register, a clock bus, an additional shift register, an NAND element, an RS flip-flop, the output of which is connected to the information input of the additional register shift, the output of the first digit of which is connected to the information input of the main shift register, and the inverse output of the last digit is connected to the first input of the AND-NOT element and the R-input of the RS flip-flop, the S-input of which is connected to the output of the AND-NOT element, the second input of which connected to the clock bus, and the clock input of the additional shift register is connected to the clock bus. In this device, the duration does not change and is equal to the number of register bits multiplied by the period of the clock signals.

The disadvantage of this device is that it is operable for periodic signals with a duration that differs by no more than one period of the input frequency. When changing the duration on the input bus for more than one period, the device is not operational. In addition, when receiving information via galvanic communication, there are problems in changing the duration due to the difference in turn-on and turn-off delays at galvanic isolation, cable network, and integrated circuits.

The objective of the invention is to increase the stability of the duration of the output signals in asynchronous devices with different durations of the input signals.

The problem is solved by the fact that an asynchronous input device is proposed, containing input, output and synchronizing buses, a shift register. Additionally, a D-trigger, 2AND and 2OR elements are introduced into it.

In FIG. 1 shows a block diagram of the proposed device, where:

1 - input bus,

2 - synchronizing bus,

3 - D-trigger,

4 - shift register,

4.1 - D-flip-flop of the first bit of the shift register,

4.2 - D-trigger of the second bit of the shift register,

4.3 - D-flip-flop of the third bit of the shift register,

4.4 - D-flip-flop of the fourth bit of the shift register,

5 - element 2OR,

6 - element 2I,

7 - output bus.

The clock bus (2) is connected to the clock input of the shift register (4), which consists of four D-flip-flops of the first (4.1), second (4.2), third (4.3), and fourth (4.4) bits, and to the clock input of the D-trigger ( 3). The input bus (1) is connected to the information input of the D-trigger (3), the output of which is connected to the information input of the shift register and the first input of the 2OR element (5), the second input of which is connected to the output of the D-trigger of the second bit of the shift register (4.2), and the output - with the first input of the element 2I (6), the second input of which is connected to the inverse output of the D-flip-flop of the fourth bit of the shift register (4.4), and the output - with the output bus (7).

In FIG. 2, fig. 3 shows timing diagrams that explain the principle of operation of the proposed device.

The device works as follows.

On power-up, the D-flip-flop and shift register are set to an arbitrary state, say zero. Upon the arrival of the first pulse on the input bus along the front of the clock pulse, a single state is set at the output of the D-flip-flop (timing diagram 3). Further, according to the following clock pulses, the bits of the shift register also go into a single state (time charts 4.1, 4.2, 4.3), and the inverse output of the last bit goes to zero (time chart 4.4). The output of the element 2OR (5) is set to a single state, equal to the sum of the signals from the elements of the D-trigger (3) and the D-trigger of the second bit of the shift register (timing diagram 5). The inverse output of the D-flip-flop of the last bit of the shift register limits the duration of the output pulse at the output of the element 2I (6) and on the output bus (7) (timing diagram 6).

This makes it possible to form a stable output signal with a duration of 4 periods of the input frequency, with an input signal duration with an error of ± 1 period of the clock frequency, due to the formation of a long pulse at the output of the 2OR element (5) and its limitation by the D-trigger of the last bit.

In FIG. 2 shows an example of operation with an input signal duration equal to 3 periods of the input frequency. By summing the signals from the D-trigger (3) and the D-trigger of the second bit of the shift register, a signal is generated at the output of element 2OR (5) with a duration of 5 periods of the input frequency, while the D-trigger of the last bit of the shift register receives an input signal for the fourth period of the clock input frequency and from its inverse output, the signal to the element 2I (6) is stopped, which limits the duration of the output signal to exactly four periods of the input frequency. The circuit works similarly for input signals with a duration of more than 4 periods of the input frequency (Fig. 3 shows an example of operation with an input signal duration of 5 periods of the input frequency).

The technical result of the proposed device is to increase the stability of the duration of the output signals for different durations of the input signals in asynchronous devices.

Thus, an asynchronous input device is claimed, containing input, output and clock buses, a shift register, where the clock bus is connected to the clock input of the shift register, in which a D-flip-flop, elements 2I and 2OR are additionally introduced, the clock bus is connected to the clock input D- trigger, the input bus is connected to the information input of the D-flip-flop, the output of which is connected to the information input of the shift register and the first input of the 2OR element, the second input of which is connected to the output of the second bit of the shift register, and the output to the first input of the 2I element, the second input of which is connected with the inverted output of the fourth bit of the shift register, and the output - with the output bus.

Claims (1)

An asynchronous input device containing an input, output and clock bus, a shift register, where the clock bus is connected to the clock input of the shift register, characterized in that a D-flip-flop, 2I and 2OR elements are additionally introduced, the clock bus is connected to the clock input of the D-flip-flop, the input bus is connected to the information input of the D-flip-flop, the output of which is connected to the information input of the shift register and the first input of the 2OR element, the second input of which is connected to the output of the second bit of the shift register, and the output to the first input of the 2I element, the second input of which is connected to the inverse the output of the fourth bit of the shift register, and the output - with the output bus.

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