SU1599899A1 - Parallel asynchronous register built about cmis transistors - Google Patents

Abstract

The invention relates to computing and can be used in the construction of asynchronous devices for receiving and storing information. In order to simplify the register containing memory cells 1-3, consisting of inverters 4 and 5, a key element on an N-type transistor 6 and a switching element on two transistors P-type 7 and 8, and a control trigger 9 on the AND element -Or-NOT 11 in the inverter 10, the drains of transistors 6.8 and the output of inverter 5 are connected to the input of inverter 4, the output of which is connected to the input of element 11. The output of the latter is connected to the gate of transistor 8 and the input of inverter 12, the output of which is connected to output 14 write register indications, the input 13 of which write resolution is connected to 6.7 Shutter cell transistors 1-3 and 15-17 data inputs - with the sources of transistors 7 cells 1-3 and 12. The input of the inverter 1 yl.

Description

The invention relates to computer technology and can be used to build asynchronous devices for receiving and storing information.

The purpose of the invention is to simplify the register. The drawing shows a register scheme. The register contains memory cells 1-3, each of which consists of the first 4 and second 5 inverters, a key element on the n-type transistor 6 and a switching element consisting of the first 7 and second 8 p-type transistors, and a control trigger 9, consisting from inverter 10 and the element AND — OR — NOT 11.

The drawing also shows a bus of zero potential 12 of the register, a recording permission input 13, a recording indication output 14, information inputs 15-17 and register outputs 18-20.

The register operates as follows.

In the initial state, a high potential is applied to the write enable control input 13, which opens the transistor 6 and closes the transistor 7. At the same time, a low potential appears at the inverter 4 input (since the channel resistance of transistor 6 is less than the channel resistance of the p-type transistor of inverter 5, it “drags "Inverter 5), and at the output of inverter 4 - high potential, ie memory cells 1, 2 and 3 go to the zero state. As a result, low potential appears at the output of element 11, which opens transistors 8, and at the output of inverter 10, i.e. 14 register output - high potential

After the potentials corresponding to the values of the bits of the recorded code are established at the information inputs 15-17, a low potential is applied to the control input 13, which closes the transistors 6 of cells 1-3 and opens the transistors 7 of these cells. Through open transistors 7 and 8, information from inputs 15-17 goes to the inputs of inverters 4 cells 1-3, while if 0 is written in the cell, i.e. low potential is applied to the corresponding information input, then its state does not change and the potential remains high at the inverter 4 output. If 1 is written in the cell, i.e. high potential is applied to the corresponding information input, then high potential is established at the input of inverter 4 (since the resistance of the chain of transistors 7 and 8 is less than the resistance of the p-type transistor of inverter 5, this chain “pulls” inverter 5), and at the output of inverter 4 low potential. Only after the information is written to all memory cells 1-3 and the potential at the outputs of their inverters 4 becomes opposite to the potential at the corresponding information inputs 15-17, element 11 will switch over and a high potential will appear at its output, which will close the transformers of 8 cells 1-3, i.e. cut them off from the information inputs 15-17. After that, the inverter 10 will switch and at its output, i.e. Output 14 of the register will have low potential, which indicates the completion of transients in this phase of the register.

After that, the signals at the information inputs of 15-17 memory cells 1–3 can be arbitrarily changed so that by the time the next code is written to the register, these potentials will be set to correspond to the bits of the recorded code.

Before a new code entry, the register must be returned to its original state. This process is carried out by applying a high potential to the control input 13, as a result of which transistors 7 of memory cells 1-3 are closed and their transistors 6 are opened and low potentials appear at the inputs of inverters 4 of these cells, which cause the appearance of high potentials at the outputs. inverters 4 memory cells 1-3. After a high potential appears at the outputs of inverters 4 of all memory cells 1-3, the switching of element 11 occurs, the output of which appears low potential, opening transistors 8 memory cells 1-3, and then switching the inverter 10 and its output, t. e. The output 14 of the register will have a high potential, which indicates the completion of transient processes when the register returns to its original state.

The cost of equipment for the implementation of the proposed register is 13p + 6 KMDP transistors, where η is the number of register memory cells. In the well-known register, this value is 26p- | -22.

Claims (1)

Claim A parallel asynchronous register on CMOS transistors containing n memory cells, each of which consists of two inverters, the input and output of the first connected respectively to the output and input of the second, and a control trigger containing an AND — OR — NOT element and an inverter whose input connected to the output of the AND — OR — NOT element, and the output to the first inputs of the η groups of the AND — OR — NOT element, the second inputs of which are connected to the η inputs of the (n + 1) th group of this element and are the corresponding information outputs of the register, characterized the fact that In order to simplify the register, each memory cell contains a key element on an η-type transistor, the source of which is connected to the bus of the register potential zero, the drain is connected to the input of the first inverter of this memory cell, and the gate is connected to the (n + 1) -th input (n + 1) th group of the AND — OR — NOT element of the control trigger and is a register enable input, and a switching element containing two p-type transistors, the source of the first p-type transistor being connected to the second input of the corresponding group of the AND — OR — NOT , shutter - with shutter transistor η-type is a key element of a given memory cell, and the drain is connected to the source of the second p-type transistor, the gate of which is connected to the output of the AND — OR — NOT control trigger element, and the drain is connected to the input of the first inverter of this memory cell, the output of which is connected to the second the input of the corresponding group of the AND — —OR — NOT element of the control trigger, the third input of which is connected to the source of the first p-type transistor of the switching element of this memory cell, the inverter output of the control trigger is the 5th output of the register record indication, the resistance of the channels of open transistors of p- and n-types of the second inverter of each memory cell is k — 1 times greater than the resistance of the channels of 10 open transistors of the corresponding key switching elements of this memory cell, k is the ratio of the register voltage to the threshold voltage of the first inverter of this memory cell .