SU1665405A1 - Parallel asynchronous register designed with cmis transistors - Google Patents

Abstract

The invention relates to computing and can be used in the construction of devices for receiving and storing information. In order to simplify the register containing memory cells (PL) 1-3, consisting of inverters 4, 5, a key element on an N-type 6 transistor and a block element on a P-type 7 transistor, a control trigger 8 on I-elements. OR - NOT 9 and AND - NOT 10, logic element 13 on P-type 14 and N-type transistors 15, 16, AND elements are inserted in it - NOT 11, 12 and switching element on P-type transistor 17. And element inputs - NOT 11 is connected to the control 18 and informational 23 - 25 outputs of the PL 1 - 3, and the output - to the input of the AND element - NOT 10 of the controlling trigger 8, the output of the AND element - OR - NOT 9 otorrhea is connected to a first input of AND - NOT 12. A second input of AND - NOT 12 is connected to the output of the element 13, and the output is the output 22 indicating the moments termination transients register. In this case, the source of the P-type transistor 17 is connected to its supply voltage bus, the gate is connected to the control input 18, and the drain is connected to the power input of the inverters 5 ЯП 1 - 3. 1 Il.

Description

The invention relates to computing and can be used in the construction of devices for receiving and storing information.

The purpose of the invention is to simplify the register.

The drawing shows a register diagram.

The register contains memory cells 1–3, each of which consists of a first 4 and a second 5 inverters, a key element 6 on an n-type transistor and a blocking element 7 on a p-type transistor, a control trigger 8, made on AND-OR elements -NOT 9 and NAND 10, elements NAND 11 and 12, a logic element 13, made on o-type 14 and n-type transistors 15 and 16, and a switching element on a p-type transistor 17.

The drawing also shows the control input 18, information inputs 19-21, output 22 indicating the register transient end moments, information outputs 23-25, supply voltage bus 26 and zero potential bus 27.

The register works as follows.

In the initial state, a high potential is supplied to the control input 18 of the register, which opens the transistor 6 of each memory cell 1–3 and closes the transistor 17, and at the output of the element 13, i.e. There is also a high potential in the drain of its transistors 14-16, which closes the transistor of 7 memory cells 1-3. In this case, a low potential appears at the input of the inverter 4 of each memory cell 1–3 (the inverter 5 of each memory cell 1–3 is disconnected from the register power supply bus by the closed transistor 17 and does not prevent this), and at the inverter 4 output it is high potential i.e. memory cells 1 to 3 are in the zero state. As a result, at the output of element 11 there is a low potential, at the output of the element AND-HE 10 of the control trigger 8 - a high potential, and at the output of the element AND-OR-HE 9 of this trigger - a low potential that enters the input of the element AND-HE 12 and there is a high potential at its output, i.e. At the output 22 of the register in the initial state there is a high potential, indicating the readiness of the register to receive codes from information inputs 19-21.

After the potentials corresponding to the bits of the writeable code are set at the information inputs 19-21 of the memory cells 1–3 of the memory, a low potential is supplied to the control input 18 of the register, which through the open transistor 15 of the element 13 goes to the last output, from where the gates of transistors 7 memory cells 1–3, transistors 6 of which are closed by low potential from control input 18 of the register, transistors 7 memory cells 1–3 open. and information from information inputs 19–21 is fed to the inverter inputs of 4 cells 1 -3 memories, pr Here, if the memory is recorded in a null cell, i.e. low potential is applied to the corresponding information input, its state does not change and at the output of inverter 4 of this memory cell the potential remains high. If a unit is written in the memory cell,

5 i.e. a high potential is applied to the corresponding information input, then a low potential appears at the output of the inverter 4 of this memory cell, since a high potential is established at its input

0 (the resistance of the transistor 7 is less than the resistance of the n-type transistor of the inverter 5 of this memory cell and the transistor 7 inverts the inverter 5), after the information is written into all cells 1-3

The 5 memories and the potentials at the outputs of their inverters 4 will become opposite to the potentials at the information inputs 19-21, switching element 9 of the control trigger 8 will occur. Note that when

0, the set of values at information inputs 19-21, which do not require switching of memory cells 1–3, trigger element 9 of the trigger is caused only by the appearance of a low potential at the output of element 13.

5 At the same time, a low potential applied to the control input 18 of the register causes a high potential at the output of the element AND-NOT 11. Switching the AND-OR-NOT 9 and I0 NOT 11 elements will, in turn, trigger the AND-element NOT 10 control trigger 8, the output of which turns a low potential, closes the transistor 15 and opens the transistor 14 of the element 13, resulting in a high potential at the output of the last (the transistor 16 of this element is closed by a high potential from the output of the AND-OR element -NOT 9). Thus, at both inputs

0 of the element 12 in the vehicle has high potentials from the outputs of the elements AND-OR-NOT 9 and 13. That will cause the appearance of a low potential at the output of the element AND-NOT 12. Ie control output 22 of the register, which is

5 sign of completion of the recording process. In addition, a high potential from the output of element 13 will close the transistors of 7 memory cells 1–3, i.e. make these cells insensitive to potential changes at information inputs 19-21: cut off

these memory cells from information inputs.

After that, the signals on the information inputs 19-21 of memory cells 1–3 can be changed arbitrarily so that by the time the next code is written, the potentials corresponding to the values of the bits of the code to be written are set to the register

Before a new code is written into the register, the latter must be returned to the initial state, for which a high potential is applied to the control input 18 of the register. This will lead to the opening of transistors of 6 memory cells 1–3 and the closing of transistor 17, which in turn will cause the appearance of low potentials at the inverter inputs of 4 of these cells, and then high potentials at the outputs of these inverters. After all the cells 1–3 of the memory go to the zero state at the output of the NANDI element 11, the potential is low, which causes the appearance of the output of the NANDI element 10 of the control trigger 8, and then the low potential at output element AND-OR-NOT 9 of this trigger. The latter will result in the appearance of a high potential at the output of the NAND 12 element, i.e. at the control output 22 of the register, which is a sign of the completion of the transients when the register is returned to the initial state.

The equipment costs for the implementation of the proposed register are (12p + 18) CMD transistors, where n is the number of register memory cells. In the known register, this value is equal to (26n + 22), i.e. There is a simplification of the parallel asynchronous register for any number of memory locations.

Claims (1)

Claims of the invention A parallel asynchronous register on CMOS transistors containing memory cells, each of which consists of two inverters, the input and the output of the first inverter connected respectively to the output and input of the second inverter, controlling the trigger on the AND-OR-AND elements NAND, the first input of the NAND element is connected to the output of the AND-OR-NOT element, and the output is connected to the first inputs of the n groups of the AND-OR-NOT element, the second inputs of which are connected respectively to the outputs of the first inverters of the respective memory cells 1 and are information inputs of the register, and a logic element made on two n-type transistors and a p-type transistor 5, the gate of which is connected to the gate of the first n-type logic element transistor and the output of the N-control trigger, and the drain - with the drain of the first n-type transistor logic 0 element, characterized in that, in order to simplify the register, it contains a switching element made on a p-type transistor and an AND-NOT element, and the output of the first element AND-NO is connected to the second input of the AND-NOT control element trigger, n inputs - with the outputs of the first elements of the NOT corresponding memory cells, and the (n + 1) -th input is the control input of the register, the output 0 of the second element AND-NOT is the output of indication of the end of the register transients, the first input is connected to the output of the element AND-OR-NOT of the control trigger and the drains of the first and 5 of the second n-type transistor of a logical register element, the source of the second n-type transistor is connected to the source of the p-type transistor of the logic element and (n + 1) -th input of the first NAND element, and the gate with 0 by the output of an AND-OR-NOT control trigger, and the source of the p-type transistor of a logic element is connected to the register supply voltage bus, and an element is entered into each cell of the register’s memory 5 interlocks on the p-type transistor and the key element on the n-type transistor, the source of which is connected to the register potential zero bus, the drain to the input of the first inverter of this memory cell, and the gate 0 - with (n + 1) -th input of the first NAND element and the gate of the p-type transistor of the switching element, the source of which is connected to the register supply voltage bus, and the drain is connected to the power input of the second inverter each memory terminal, source the p-type transistor of the blocking element of each memory cell is connected to the third input of the corresponding group of the AND-OR-NOT element and is the corresponding information 0 is the input of the register, the drain is connected to the input of the first inverter of the given memory cell, and the gate is connected to the second input of the (n + 1) -th group of the AND-OR-NOT control trigger element.