SU1587593A1 - Mis-transistor-base parallel asynchronous register - Google Patents

Abstract

The invention relates to computing and can be used to build asynchronous devices for receiving and storing information. In order to simplify the register containing memory cells 1 - 3, each of which consists of inverters 4, 5 and logic element 6, executed on a load 7 and key 8-10 MOS transistors, and a control trigger 11, consisting of an inverter 12 and the element AND-OR-NOT 13, the sources of the transistors 8 and 10 of the cells 1 - 3 are connected to the control input 17 of the register, and the gates of these transistors are connected respectively with the output of the inverter 4 and the control output 18 of the register. 1 il.

Description

The invention relates to computer technology and can be used to build asynchronous devices for receiving and storing information.

The purpose of the invention is to simplify the register.

The drawing shows a register scheme.

The register contains memory cells 1-3, each of which consists of the first 4, second 5 inverters and logic element 6, made on load 7 and first 8, second 9 and third 10 key MOS transistors, control trigger 11, consisting of inverter 12 and the element AND-OR-NOT 13. The register also has information inputs 14-16 and control input 17 and output 18.

Parallel asynchronous register works as follows.

In the initial state, at the control input 17 of the register there is a high potential, 8 as a result of which there will also be high potentials at the outputs of elements 6 cells 1-3, at the outputs of their inverters 4 low potentials, and at the outputs of inverters 5 there will be high potentials, at the output of control element 13 trigger 11 low potential, and at the output of its inverter 12, i.e. at the control output of 18 registers, - high potential.

After the single-phase signals corresponding to the bits of the recorded code are received at the information inputs 14-16 of the memory cells 1-3, a low potential is applied to the control input 17 of the register. At the same time, at the output of element 6 of each memory cell 1-3, a value is set that is opposite to the value at the corresponding information input 14-16, at the output of inverter 4 - corresponding to this value, and at. the output of the inverter 5 is the opposite value at the corresponding information input 14-16, as a result of which a high potential appears at the output of the element 13 of the control trigger 11, and at the output of its inverter 12, i.e. at the control output 18 of the register there is a low potential, which indicates the completion of transients when writing the code to the register and setting the paraphase code at the outputs of inverters 4 and 5 of cells 1-3 of memory.

Low potential on managing you. During register 18, it closes transistors 10 and makes memory cells 1-3 and control trigger 11 insensitive to changes in signal values at information inputs 14-16 (cuts off the register from information inputs).

After that, the signals at the information inputs of 14–16 cells 1–3 of the memory can be arbitrarily changed so that, by the time the next code is written in the 5th register, the values corresponding to the bits of the recorded code are set on these inputs.

Before a new code entry, the register must be returned to its initial state, 10 for which high potential is applied to its control input 17. This causes the appearance of the same potential at the outputs of the elements 6 cells 1-3 memory, then low potential at the outputs of inverters 4 and, finally, 15 high potential at the outputs of inverters 5 of these cells. As a result, the low potential appears at the output of the element 13 of the control trigger 11, and at the output of its inverter 12, i.e. on the control 20 output 18 of the register, there is a high potential, which indicates the completion of transient processes when the register returns to its initial state.

It follows from what has been said that when controlling the process of writing information to the register and returning it to its original state with the help of a signal at control output 18, the influence of the delay spread of the register elements on its operation is eliminated.

Claims (1)

30 claims A parallel asynchronous register on MOS transistors containing η memory cells, each of which consists of the first and second inverters and a logic element consisting of a load and three key transistors, the drain of the load transistor connected to the register power bus and the source to the CO drain the first and second key transistors 40 of the logic element and the input of the first inverter, the output of which is connected to the input of the second inverter and the gate of the first key transistor of the logic element, the source of the second of the first transistor which is connected to the drain of the third key transistor, and the gate is the corresponding information input of the register, and the control trigger, consisting of an inverter and an AND-OR-NOT element 50, the output and the first inputs of η groups of which are connected respectively to the input and output of the control inverter trigger, and the second inputs with inputs (n + 1} -th group of this element, exc and tea 55'щ and the second with the fact that, in order to simplify the register, the second inputs of the n groups of the AND-OR-NOT element of the control trigger are connected with the outputs of the second inverters respectively of the corresponding memory cells are the information outputs of the register, and the third inputs are connected to the gates of the secondary key transistors of the logical elements of the corresponding memory cells, the sources of the first and third key transistors of the logical elements of the memory cells 5 and (n + 1) -th input (n + 1) - group II of the element OR-NOT of the control trigger are the control input of the register, and the gates of the third key transistors of the logical elements of the memory cells and the inverter output of the control trigger are the control output of the register.