SU1624530A1 - Parallel asynchronous register - Google Patents

Abstract

The invention relates to computing and can be used in the construction of asynchronous digital computers. In order to simplify a parallel asynchronous register containing memory cells 1–3, each of which consists of an inverter 4 and a logic element 5, made on the load resistor 6 and the MOS transistors 7–9, the OR-HE element 21 and the control trigger 10, consisting of an inverter 11 and a logic element 12, made on the load resistor 13, key 14, and functional 18-20 MOS transistors, a switching element is introduced into the register on the MOS-transistor 22, the gate of which is input 24 of writing the register , but the output of the inverter 11 of the control trigger 10 is the output 23 of the recording indication. 1 il. Ё About go 4 joint ventures with about

Description

The invention relates to computing and can be used in the construction of asynchronous digital devices.

The aim of the invention is to simplify the register.

The drawing shows the scheme of the proposed register.

The register contains memory cells 1–3, each of which consists of an inverter 4 and a logic element 5, made on the load 6 and first 7, second 8 and third 9 MOSFETs, controlling the trigger 10, consisting of inverter 11 and of the logic element 12, made on the load 13, the key 14 and groups 15-17 of the three functional MOS transistors 18-20, the element AND NOT 21 and the switching element on the transistor 22. The drawing also shows the output 23 of the recording indication, the resolution 24 records, information inputs 25-27 memory cells, shea and 28 a power, ground potential bus 29.

Inlet 24 and outlet 23 are controllers.

Parallel asynchronous register works as follows.

In the initial state at the control input 24 of the register there is a low potential, as a result of which the transistor 22 is in the closed state and at the outputs of the elements of 5 cells 1-3 there will also be high potentials, at the outputs of their inverters 4 low potentials, at the outputs of the element OR NOT 21 is a high potential, which opens up the transistor 14 and sets low potential at the output of element 12, and high potential at the output of inverter 11.

After the information inputs 25-27 of the memory cells 1-3 receive single-phase signals corresponding to the bits of the code being written, a high potential is applied to the control input 24 of the register, which leads to the appearance of a zero value at the output of the element OR NOT 21, with the result that the transistor 14 goes into the closed state. In addition, a high potential at the input 24 opens the transistor 22 and a low potential arrives at the input of the element 5 of each memory cell, as a result of which its output is set to the opposite value of the corresponding information input 25-27, which leads to the appearance of the inverter 4 of each value cell coinciding with the values at the corresponding information input 25-27. In addition, if the output of the inverter 4 and the corresponding information input is zero, then the transistors connected to these inputs

in element 12, they are closed, which prevents the low potential from passing to the output of element 12. As a result, high potential is output at the output of element 12, and low potential at the output of inverter 11 and control output 23, which indicates the completion of transients during recording code in the register and the installation of the para-phase code at the outputs of the inverters 4 and the elements of 5 memory cells 1-3.

Note that the low potential at the control output 23 of the register closes the transistors 9 and makes insensitive cells 1-3 and the control trigger 10 change the values of the signals at the information inputs 25-27 (cuts off the register from the information inputs).

Thereafter, the signals at the information inputs 25-27 of memory cells 1-3 can be arbitrarily changed so as to

so that by the time the next code is written into the register, these inputs are set to values corresponding to the bits of the code being written.

Before a new code entry, the register must be returned to the initial state, for which a low potential is applied to the control input 24, which closes the transistor 22. This causes a high potential at the outputs of the 5-cell cells.

memory 1-3, then a low potential at the outputs of the inverters 4 and, finally, a high potential at the output of the OR-NOT 21 element. As a result, the output of the element 12 of the control trigger 10 appears low

the potential, and the output of its inverter 11, i.e., at the control output 23 of the register, is a high potential, which indicates the completion of transients when the register returns to its initial state.

It follows from the above that in the proposed register, as well as in the prototype, controlling the process of recording information in the register and returning it to its original state using the signal at the control output 23 eliminates the influence of the spread of the register elements on its operation. .

Estimating the complexity of the parallel 5 asynchronous register by the number of MOS transistors necessary for its realization, we get (1 On + 7), where n is the number of register memory cells. In the prototype, this value is (16p + 17), that is, e. There is a simplification of the register for any item.

Claims (1)

Claims of the invention A parallel asynchronous register on MOS transistors, containing memory cells, each of which consists of an inverter and a logic element, consisting of a load and three functional transistors, the drain of the load transistor connected to the register power supply and the source with the drain of the first and second functional transistors of the logic element and the input of the inverter, the output of which is connected to the gate of the first functional transistor of the logic element, the source of the second functional trap The resistor is connected to the drain of the third functional transistor, respectively, and the gate is an information input of the memory cell, an OR-NOT element and a control trigger consisting of an inverter and a logic element containing load and key transistors and n groups of three functional transistors, with the drain and the gate of the first functional transistor of each group connected respectively to the input and output of the control inverter inverter, and the source to the drain of the second functional transistor e group whose gate is connected to the output of the inverter corresponding memory cell, the drain and the source of the load transistor of NAND gate control flip-flop are respectively connected to The power bus and the drain of the key transistor, the load transistor drain is connected to the input of a control trigger inverter, characterized in that, in order to simplify the registers, a switching element is introduced on the transistor, the gate of which is a recording enable input, and the source and drain are connected to the bus zero potential and the origins of the first and third functional transistors of the logic elements of each memory cell, the gates of the third functional transistors of which are connected to the output of the control inverter three and are the output of the register recording indication, the source and the gate of the key transistor of a control element logic gate are connected respectively to the register potential zero bus and to the output of the OR-NOT element, whose inputs are connected to the outputs of the inverters of the memory cell and the gate of the transistor of the switching element, the drain and source of the third functional transistor of each group of the logic element of the control trigger are connected respectively to the drain and the gate of the second functional transistor of this g The group, the source of which is connected to the gate of the third functional transistor of this group and with the gate of the second functional transistor of the logic element of the corresponding memory cell.