SU1474738A1 - Memory - Google Patents

Abstract

The invention relates to computing and can be used in the construction of random access memory devices on CMD transistors. In order to increase the speed of the storage device by organizing its work on the real element delays by indicating the end points of transients in the device, the elements AND-HE 17, AND-OR-HE 18, inverter 19, p-type transistors 6 and 7 and p-type transistors 12-15. Moreover, the output of the element 17 is connected to the gates of the transistors 6,7 and the inputs of the element 18, and its inputs to the inputs of the element 18, the other inputs of which are connected to the information outputs 21,22 and the inputs 23,24 of the device, to the control 25, 26 inputs of the device and with its control output 27, which is connected to the output of the inverter 19, the input of which is connected to the output of element 18. 1 sludge.

Description

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The invention relates to computing and can be used in the construction of random access memory devices on a CMOS transistor pax.

The aim of the invention is to increase the speed of the storage device by organizing its work according to the actual delays of the elements by indicating the end points of the transient processes in the device.

The drawing shows a diagram of a storage device.

The device contains 1 memory elements, key elements made on n-type MIS transistors 2 and 3, a writing unit consisting of four n-type MIS transistors 4-7, a mode setting unit consisting of eight P-type MOSFET transistors 8-15 and two resistors 16, elements AND-NOT 17, AND-OR-NOT 18, inverter 19. The address inputs 20, zero and single information outputs 21 and 22 and inputs 23 and 24, write control inputs 25 and read 26 and device ready output 27, power bus 28 and device zero-potential bus 29.

 The storage device operates as follows.

In the storage mode, the low voltage potentials covering the transistors 2 and 3 are fed to the address inputs 20 of all the memory elements 1, the write control 25 and read 26 and zero 23, and the single 24 data inputs are also fed to the low potentials. As a result, transistors 4, 5 and 8, 9 are closed and transistors 10, 11, 14 and 15 and 12 and 13 are open, which leads to the appearance of high potentials at zero 21 and single 22 you

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device moves. The latter cause a low potential at the output of element 17, a high potential at the output of element 18 and, finally, a low potential at the output of the inverter 19, i.e. at the control output 27.

 In the mode of reading information from element 1, high potential is applied to address input 20, which opens transistors 2 and 3, and low potential from zero or single input-output of this element 1 arrives at output 21 or 22. At the same time, high potential is fed to input 26 of control that covers the transistors 10 and 11. If the low potential is set at the 2G output, then the transistor 9 will be open and the output 22 will be a high potential, closing the transistor 8. If the low potential is set at the output 22, then the transistor 8 will be opened and Exit 21 will be a high potential, closing transistor 9. In both cases, the output member 17 to Vits high potential at the output of element 18 - a low potential, and the output of the inverter 19, i.e., at the device control output 27, a high potential, which is a sign of the completion of transients in this mode.

In the information recording mode, as in the previous case, a high potential is applied to the memory element 1, opening transistors 2 and 3, and a low potential from the zero or single input-output of this memory element 1 is output 21 or 22. At the same time, a high potential is applied to the device control input 25, covering the transistors 14 and 15. Further, as in

read mode, one of the pair of transistors 8 and 9 opens, and the other remains closed, and a high potential appears at the output of element 17, opening transistors 6 and 7. In addition, information written to memory element 1 is supplied to information inputs 23 and 24 ti i A high potential is established at one of these inputs. If this potential is set at input 23, transistor 6 opens and transistor 12 closes, resulting in a low potential at output 21. If a high potential is established at the input 24, then the transistor 7 opens and the transistor 13 closes, with the result that a low potential appears at the output 22.

If the information set at information inputs 23 and 24 coincides with the previously recorded in element 1, then the state of the latter does not change even after a high potential appears at the output of element I7, a low potential appears at the output of element 18, and Inverter 19, i.e. at the control output 27 of the device, a high potential, which, as in the read mode, is a sign of the completion of transients.

If the information set on information inputs 23 and 24 is opposite to that previously recorded in item 1, then the latter is switched. In this case, despite the high potential at the output of the element 17, the switching of element 18 does not occur until the required state is established in element 1. In this case, at first, both potentials 21 and 22 show low potentials, then as a result of recording information element 1 at one of outputs 21 or 22 will recover a high potential. Only after this, the output potential of the element 18 is low potential and, at the output of the inverter 19, i.e. At the control output 27 of the device, high potential, which is a sign of the completion of transients in the recording mode.

In order to return the device to storage mode, it is necessary to set low potentials at address input 20 and control inputs 25 and 26, as well as at information inputs

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23 and 24. At the same time, transistors 2-5 are closed and transistors 10, 11 and 14, 15 are opened, as a result of which high potentials are restored at both outputs 21 and 22, low potential is output at element 17, then output 18 - high potential and, finally, at the output of the inverter 19, i.e. at the control output 27 of the device, a low potential, which is a sign of the completion of transients in the storage mode.

In the case of delaying the closing of transistors 2 and 3, for example, due to the delay of the low potential setting at address input 20, there is no distortion of information in memory element 1, since the outputs 21 and 22 are connected by open transistors 10, 11 and 14, 15 to the bus power through resistors 16, which allows the potential to be kept low at the corresponding output 21 or 22 until transistors 2 and 3 are closed.

A sign of the completion of transients in the device when changing modes is a change in potential at the control output 27 of readiness. This signal appears at the end of the actual transients at any delay values of the device transistors. Thus, in the device, the end points of transients are displayed, which allows organizing its work according to real delays and, consequently, increasing its speed.

From the above description of the memory operation, it can be seen that in any of the modes the steady state is characterized by the fact that in each of the circuits of the device between its power supply bus and the zero potential bus there is at least one closed MOSFET transistor that provides in the proposed device as low energy consumption as in the known.

Claims (1)

Invention Formula A storage device containing memory elements and corresponding-. pairs of key elements, each of which is made on an n-type transistor, and the sources of the first and the second n-type transistors are connected respectively to the zero and single inputs-outputs of the memory element, the gates are the corresponding address input of the device, and the drains are the zero and single information outputs of the device, the recording unit, consisting of the first and second AND-NOT and the first inputs of each group AND element AND-OR-NOT, the output of which is connected to the input of the inverter, the output of which is connected to the second input of the first group AND element AND-OR-NOT and is the device ready output, are entered into the mode setting unit The first and second resistors and n-type transistors, the gates of which are 10th, sixth, seventh and eighth p-type transistors, the drain of which is connected to the sources of the first, second, third and fourth p-type transistors, respectively, are the zero and single information inputs of the device, and the drains are connected to the drains of the corresponding n-type transistors of the key elements, the block for setting the operating modes of the fourth transistor of the p-type connection, consisting of four Nene transistors with the second input of the second group II p-type, with the third and fourth transistors of the p-type transistors being the input for controlling the reading of the AND-OR-NOT device, the seventh and eighth gates of the p-type transistors are connected to the second inputs of the third and the first and second trances of the fourth group AND AND-OR-NOT element p-type resistors are connected respectively to the drains of the second and fourth and first and third transistors of the p-type and to the drains of the first and second transistors of the n-type key elements. characterized by that, in order to improve the speed of the device, an AND-OR-NOT element, an inverter and an AND-NOT element are introduced into it, the third and fourth n-type transistors are introduced into the recording unit, the outlets of which are connected respectively to the sources of the first and second transistors of the 5th - na, origins - with a tire of zero potential, and closures - with the output element p-type transistors, the drain of which is connected to the sources of the first, second, third and fourth p-type transistors, respectively, the fourth transistor of the p-type is connected to the second input of the second group And the fourth transistor of the p-type is connected to the second input of the second group And element AND-OR-NOT, the gates of the seventh and eighth p-type transistors are connected to the second inputs of the third and and are the control input of the device for recording, the sources of the fifth and sixth p-type transistors are connected to the device power bus and through the first and second resistors to the sources of the seventh and eighth p-type transistors, the gates of the fifth and sixth p-type transistors are connected to the third inputs of the third and fourth groups AND element AND-OR-NOT and with the gates of the first and second transistors of the n-type recording unit, the drains of which are connected to the fourth- | the inputs of the fourth and third groups AND of the AND-OR-NOT respectively, and with the inputs of the AND-NOT element.