SU1615807A1 - Igfet-transistor parallel asynchronous register - Google Patents

Abstract

The invention relates to deduction technique and can be used in asynchronous information storage devices. In order to simplify a parallel asynchronous register containing memory cells 1-3, consisting of an OR-AND-NO element 5 and a logic element 6, executed on a load 7 and key 8-10 MOS transistors, and a control trigger 12, The fourth key transistor 11 is inserted into the logic element 6 of each memory cell, the control input 15 of the register is connected to the input of the first group of the element 5, and with the gate of the transistor 11 memory 1-3. , the drain of which is connected to the source of the transistor 8, the gate of which is connected with the output of element 5 and the input of the trigger 12, and the drain with the source of the load transistor 7, the input of the second group of element 5 and another input of the trigger 12, the outputs of which are connected to the control output 19 of the register and the first input of the third group of element 5 and the gates of transistors 9 and 10 elements of 6 memory cells 1-3, informational inputs 16-18 of which are connected to the second input of the third group of element 5 and the source of transistor 10 of element 6 of these memory cells. 1 il.

Description

The invention relates to computing and can be used in asynchronous information storage devices.

The purpose of the invention is to simplify the register.

The drawing shows a register diagram.

The register contains 1–3 memory cells, a zero potential bus. Each memory cell consists of an AND / 1I-AND-NE-5 element and a logic element 6 made on the load 7 and first 8, second 9, third 10 and fourth 11 key MOS transistors, controlling trigger 12 consisting of an inverter 13 and an AND-OR-NOT 14 element. The drawing also shows the recording resolution input 15, information inputs 16-18, recording indication output 19, information outputs 20-22, and the power bus 23. Inlet 15 and outlet 19 are controllers.

The register works as follows.

In the initial state, the register control input 15 has the value O, as a result of which the outputs of the elements 5 and 6 of all memory cells 1–3 have the values 1, the output of the element 14 of the control trigger 12 is the value O, and the output of the inverter 13, i.e. at the control output 19 of the register, the value is 1,

After the information bits 16–18 of memory cells 1–3 are set to the bits of the code to be written, the value 1 is applied to the control input 15 of the register, allowing the code to be written to the register. At the same time, if on any of the information inputs 16-18 there is a value of 1, then at the output of element 5 of the corresponding memory cell there is 3 O values, and at the output of its element 5 the value 1 is saved if at this information input If the value is O, then the output of the element 5 of this memory cell will retain the value 1, and the output of its element 6 will have the value O. When the values at the outputs of the elements 5 and 6 become opposite for all the cells 1 to 3 of the memory, T.is . after the code bits are written to all the cells 1–3 of the register’s memory, the output of the control switch trigger element 14 on the Vits 12 is 1, which cuts off the memory cells 1–3 from the information inputs 16–18 and then at the output of the inverter 13 control trigger 12, i.e. at the control output 19 of the register, the value is O, which indicates the end of the process of writing to the register.

Immediately after this, you can start changing the values on the informational inputs of the 16-18 register, preparing the bits

new code to write. Moreover, since the gates of the transistors 10 of the elements of 6 memory cells 1–3 receive O values from the control output of the 19th register, these 5 transistors are closed and do not prevent the values changing at the information inputs 16–18 of the memory cells 1–3. (do not pass to these inputs the potential of the bus 23 register, to which through the open

0 transistors 9 of these elements are connected to the drain of transistors 10).

Before making the next entry of code 5 bits of the register, it is necessary to bring it to its original state, for which

5, the value O is applied to the control input 15 of the register. As a result, the outputs of elements 5 and 6 of all the cells 1 to 3 of the memory are set to 1, then first at the output of the element 14 of the control trigger

0 12 according to Wits value O, which will remove the cut-off of cells 1 - 3 of memory from informational inputs 16-18 (in particular, 9 transceivers will close 9 cells of 6 of these memory cells, which will turn off the drains of 10 transistors

5 elements from the bus 23 register), and then at the output of the inverter 13 of the control trigger 12, i.e. at the control output-19 of the registries - the value 1, indicating the completion of the transition of the register-to the initial

0 state.

In the proposed register, as well as in the well-known register, when managing the process of recording information in the register, its return to the initial state with the help of a signal to

5, the control output 19 of the register eliminates the influence of the delay spread of the elements of the latter on its operation.

Estimating the complexity of the parallel asychronous register by the number of MOPraisers necessary for its implementation, one gets {14n + 4), where l is the hr of memory cells of the register. In the known register, this value is (16p + 17), i.e. There is a simplification of the register for any item.

Claims (1)

5 The work cycle is 6g, where m is the delay of one register element. Claims of the invention Parallel asynchronous register on MOS transistors, containing a packet of cells, each of which consists of an OR-1/1-HE element and a logic element made on a load and three key transistors, the drain of the load transistor being connected to the power bus 5 registers, and the source - with the drain of the first 5-cell transistor and from the input of the first group 3ii8fv "eHTa OR - AND - NOT and has a corresponding information output of the register, the gate of the first key transistor is connected to the output element OR-AND-NOT, the input of the second group of which is the input of register register resolution, and the first input of the third group is connected to the gate of the second key transistor of the logic element of the given memory cell and is the corresponding information input of the register, the source of the second key transistor of the logic element is connected to a bus of zero potential of the register, and a drain with a drain of a third key transistor of a logic element of a given memory cell, and a control trigger consisting of an AND-OR-NOT element and an inverter connected to the output of AND-OR-NO element, and an output, the first inputs of n element groups J-OR-NO element, second and third inputs of which are connected to the drain and gate of the first switching transistors gates corresponds to memory cells and to the inputs The (n + 1) -th group of the AND-OR-NOT control trigger, which is different in that. In order to simplify the register, the logical element of each memory cell contains the fourth key transistor, the source and drain of which are connected respectively to the drain of the third and source of the first key transistors of this logic element, and the gate to the input of the second group of the element OR - AND - NOT this memory cell the first input of the third group of which is connected to the source of the third key transistor of the logic element of the given memory cell, the gate of which is connected to the output of the control trigger inverter and is the output Superimpose register entries, and inverter input control latch is connected to the second inputs of the third element group OR - OR of each memory cell.