SU1465997A1 - High-voltage switch - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in devices i forming a sequence of signals. The aim of the invention is to simplify the device and increase its speed due to the use in the feedback circuit of a discharge cell of MOS transistors and asynchronous switching mode. The goal is achieved by introducing into the device containing, in each bit cell 1, an element SHJ-NOT 2 and an inverter 3, additionally an NCP-transistor 4 connected between the information bus 6 of the discharge cell 1 and the input control bus 7, which in turn is connected with the output control bus 5 of the next bit cell. 1 il. and S (L

Description

The invention relates to automation and computer technology and can be used in devices for generating sequences of signals.

The purpose of the invention is to simplify the device and increase its speed due to the use in the feedback circuit of the discharge cell, made on the logic elements OR-NOT, MCP transistor and asynchronous mode of switching.

The drawing shows a schematic diagram of an asynchronous distributor for three digits.

The device contains in each bit cell 1 two inverting logic elements: an OR-NOT 2 element and an inverter 3, as well as an MCP transistor 4.

The output of the OR-NOT 2 element is connected to the input of the inverter 3, the gate of the MOS transistor 4 and with the output control bus 5.

The first input of the OR-NOT 2 element is connected to the input information bus 6 and to the drain of the MSC transistor 4, the source of which is connected to the input control bus 7 of the same cell and to the second input of the OR-NOT 2. The inverter 3 output is connected to output information bus 8 bit • cell 1.

The output information bus 8 of the bit cell 1 is connected to the input information bus 6 of the subsequent bit cell, and the input control bus 7 is connected to the output control bus 5 of the same subsequent bit cell

Asynchronous distributor operates as follows.

In the initial state of the discharge cell 1, the output of the OR-NOT 2 element has a zero logic level, and the output of the inverter 3 · is a single logic level, the MOS transistor 4 is in the closed state. In the asynchronous distributor, the installation of the (£ -1) ~ th bit cell 1 is done by applying a zero logic level to the information input bus 6. At the same time, at the output of the OR-NOT 2 element, a single logic level will appear, which opens the MOS transistor 4 of this bit cell and calls the appearance of a zero logic level at the output of the inverter 3. An open MIS transformer 4 disables the input buses of the 6th and 7th (1-1) -th bit cells 1 and therefore on buses 6 and 7 the zero logic level is maintained until at least at one of the output tires: 8 (1 The 2nd) -th bit cell or 5th i-bit cell has a zero logic level. If as a result of installation of the i-th bit cell and reset of the (1-2) -th bit cell on the buses of the 8 (1-2) and 5 i-th bit cells, a single logical level appears, then a reset (1-1) -th bit cell: at the output of the OR-NOT 2 element, a zero logic level appears, the MOS transistor 4 goes into a closed state, a single logic level appears at the output of the inverter 3.

Moreover, until the i-th cell on bus 5 has a single logical level, the (x-1) -th bit cell cannot be installed: at the output of the OR-NOT 2 element of this bit cell, the zero logic level will be stored outside depending on the signal value on the bus 6.

Thus, the reinstallation of the (1-1) -th bit cell D is carried out only after the i-th bit cell 1 'is in. initial condition. Therefore, when re-initiating the operation of the asynchronous distributor before the previous cycle of its operation is completed, the subsequent wave of cell installations will not reach the previous one, since there will always be one cell in the initial state between them, which ensures the correct operation of the distributor in multiprogram mode.

A positive effect in the device is achieved through the use of only two simplest logic elements and one MOS transistor per discharge and a reduction in the number of connections between cells. The increase in performance is due to a decrease in the number of logic elements in the switching circuits and a simplification of the logic elements themselves.

Claims (1)

SUMMARY OF THE INVENTION An asynchronous distributor containing bit cells, each of which contains two inverting logic elements, the output of the first being connected to the input of the second, and the information output bus and the control input bus of the bit cell connected respectively to the information input and control output buses of the subsequent bit cell , characterized in that, in order to simplify and improve performance, an MOS transistor, the first inverting logic element, is introduced into each bit cell Execute a OR-NO element, and the second - in the form of an inverter, the inputs of OR-NO element, between which ₅ mi included MLP transistor are respectively connected with the input information and the input control tires discharge cell, the output of OR-NO element is connected to the gate of the MIS transistor of the resistor and with the control output bus of the discharge cell, and the output of the inverter is connected to the information output bus of the discharge cell.