SU970652A1 - Injection d-flip-flop - Google Patents

Description

one

The invention relates to microelectronics, in particular, to semiconductor circuits on injection-powered elements, and can be used to create an LSI.

The constructions of M5D-flip-flops on multicollector IL elements of Cl are known.

The disadvantage of this p-trigger is a large footprint.

Closest to the proposed is the D-trigger, containing the main and auxiliary triggers on many

collector collector elements, a device for tapping the current from the bases of the transistors of the main trigger in accordance with the clock signal, controlling the injection current source connected to the base of one of the transistors of the main triter and controlled by the information signal 2.

The disadvantages of the known D-trigger are low performance due to the use of a horizontal transistor for transmitting the information signal, and low noise immunity due to the fact that when the clock signal is zero, the information signal changes to the base of one of the main trigger transistors, which can lead to false switching with more noise. The purpose of the invention is to increase the speed and noise immunity of the injection D -trigger.

This goal is achieved by the fact that the injecting D-trigger, containing our main and auxiliary triggers, each of which contains two multicollector IL transistors with cross-links, the collector of the first transistor of the auxiliary

Claims (2)

The tripper is connected to the first output bus, the base of the first transistor of the auxiliary trigger is connected to one of the collectors of the first transistor main trigger, the collector of the second transistor of the auxiliary trigger is connected to the second output transistor, the base of the second transistor of the auxiliary trigger is connected to one of the collectors of the second transistor of the main trigger , and a clocking two-collector transistor, the base of which is connected to the bus of clock pulses, and the collectors of a clocking two-collector transition the stora is connected to the bases of the transistors of the main trigger, an additional L transistor is introduced, the base of which is connected to the information chinor D, triggered, and with the additional collector of the first transistor of the main trigger. The drawing shows a schematic diagram of the proposed D-trigger. D-trigger contains the main trigger 1 on a pair of And L transistors 2 and 3 with sources 4 and 5 of the injection current, respectively. Auxiliary trigger 6 on another pair of IL transistors 7 and 8 with sources 9 and 1O of the injection current, respectively. The device 11 branches of the current from the bases of the transistors of the main trigger in accordance with a certain pulse clock value 12. The device 11 consists of an IL of the transistor 13 with the injection current source 14. Let us accept its collectors 15 and 16 connected to the bases of the transistors of the main trigger transistor 17 with the source 18 current injection, and its base is connected to the information D input 19, and the collector 20 with the base of the transistor 2. The transistor 13 has one additional: tny collector 21 connected to the input of the house 19. The collector 22 of the transistor 7 is connected to the first output hydrochloric bus 23 D -triggera. The collector 24 of the transistor 8 is connected to the second output bus 25 D-three Gera. D-trigger works as follows. When the clock signal is equal to logical 1, transistor 13 is open, transistors 2 and 3 are de-energized and do not affect the state of transistor 6. D-flip-flop stores information. When negative voltage is input to input 12, transistor 13 is locked, transistors 2 and 3 begin to open. An important feature is that the main trigger is asymmetric. H 24 the drawing shows one of the possible variants of the scheme, when the asymmetry is achieved using different sources 4 and 5 of the injection current. If the signal at the D input is equal to logical O, then the transistor 17 is closed and the first turn on transistor -2. and sets the auxiliary trigger to the state corresponding to aO, 5 1. In this case, the collector 21 disconnects the main trigger from the information D input 19. If the signal at the D input equals logical 1, then the transistor 17 turns on the transistor 2 is closed, then the negative clock pulse difference turns on the transistor 3, which leads to the establishment of the auxiliary trigger 6 in the state corresponding to a, "0. In this case, the collector 26. of the transistor 3 de-energizes the transistor 2, i.e. disables the main trigger from informational D input 19. If the clock signal is equal to a logical Q, the main and auxiliary triggers store information. Thus, the information signal is transmitted to the outputs GI and 5 only when a negative voltage drop is input to input 12, i.e. This circuit performs the function of the D trigger. The proposed injection D-trigger allows you to increase the speed by 10-30%, as well as increase the noise immunity of the trigger during the zero clock pulse. Invention D-triggers containing main and auxiliary O-triggers, each of which contains two multicollector transistors with cross-links, the collector of the first transistor of the auxiliary tri1ger is connected to the first output width, the base of the first transistor of the auxiliary trigger is connected to one of the collectors the first transistor of the main trigger; the collector of the second transistor of the auxiliary trigger is connected to the second output; the base of the second transistor of the auxiliary the master is connected to one of the collectors of the secondary transistor of the main trigger, and a clocking two-collector AND L transistor, the base of which is connected to the 5-bus clock, and the collectors of the clocking two-collector transistor are connected to the bases of the transistors of the main trigger, which are different in order to increase speed and noise immunity, it contains an additional IL transistor, and the base of the first transistor of the main trigger is connected to the collector of the additional L. transistor, the base of which is it is uniform with 2A information bus and with an additional collector of the first transistor of the main trigger. Sources of information taken into account in the examination 1.Avayev N. A. and others. Large integrated circuits with injection power, Moscow, Soviet radio, 1977, fig. 5.12. 2. US patent number 419747O, cl. N OZ K 3/286, 1980 (protot (w).