SU797058A1 - Pulse shaping device - Google Patents

Description

signals through a current-limiting link consisting of parallel-connected resistors and a capacitor, two switching transistors of different types of conductivity, the emitters of which are connected to the positive and negative buses of the first power source, the collector l - with one output of the feedback resistor, and the bases are connected through similar current-limiting a link with the collector of the input transistor, an additional transistor reversely relative to the input transistor of the conduction type, an additional condensate p and an output stage, the auxiliary transistor collector is connected to the input transistor collector, the emitter of the second power supply connected to the bus, the emitter of the additional transistor is connected to the third power supply's bus, and the base is connected directly to another output of the feedback resistor and connected via an additional capacitor to bus input signals, while the collectors of switching transistors are connected to the bus output signals through the output stage, which contains two. transistors of different types of conductivity, the emitters of which are connected to the power supply buses, the base through the current limiting link is connected to the input, and the collectors to the output bus of the cascade.

FIG. 1 is a schematic diagram of a pulse shaping device in FIG. 2 is a schematic of the output stage of the device; a variant of FIG. 3 - diagram of the output stage of the device, option; in fig. 4 Diagram of device pulse voltages.

The device (Fig. 1) contains an input pnpp transistor 1, the base of which is connected to the input of the device through a current limiting element consisting of resistors 2 and a capacitor 3 connected in parallel, two switching transistors 4 and 5 of different types of conductivity, the emitter of transistor 4 connected to the negative bus of the first power source, and the transistor 5 to the positive bus of this power source E, the collectors are connected to one output of the feedback resistor 6, and the bases are connected via similar current-limiting links, resistors 7 and 8, and capacitors 9 and 10, to the collector of the input transistor 1. The collector of the additional transistor 11 is connected to the collector of the input transistor 1, the emitter of which is connected to the positive bus source Ej, the base of the additional transistor is connected to another output of the resistor b connection, the emitter is connected to the negative bus of the power source EJ, the capacitor 12 is connected between the base of the additional transistor 11 and the input of the device. The output stage 13 is connected to the collectors of the switching transistors 4 and 5, and its output is the output of the IQ device. The negative power supply bus E is connected to the positive busbars of the power sources E and E3 and to the casing. In practice, the voltage of the power source E 2 is from +1.5 to + 2V. If as the source of E to use the power source + 5V digital circuits, then between the base and the emitter of the input transistor, you must include an additional resistor. If the digital elements of negative logic are used to control the device, then the power source J :. not needed. In this case, the emitter of the input transistor is connected to the positive power source bus E3.

In order to reduce the number of power sources, instead of power sources Ex | and E, and instead of powering the output stage, one common source can be used.

The output stage can be constructed, for example, according to the symmetric emitter follower circuit.

transistors 14 and 15 different types

conductivities (Fig. 1), whose collectors are connected to the respective power supply lines, and the emitters are connected and are the output of the device. The transistor bases 14 and

0 15 are interconnected and connected to the collectors of the switching transistors 4 and 5. Such an output stage does not invert the input signal. The output stage can perform

5, the inversion of the input signal (figure 2). The circuit of this output stage is similar to the switch mode. transistors 4 and 5 (Fig. 1).

The output stage can be built in a more complex way using transistors 18-21 (Fig. 3). On connected collectors of transistors 18 and 19, a rectangular-shaped pulse output voltage is formed, inverted relative to the input voltage. On the collectors of transistors 20 and 21 a non-inverted output pulse voltage is generated. The existence of the outputs of one

0 devices of both inverted and non-inverted output impulse voltages can almost halve the number of devices when controlling single-line

5 CCD image sensor.

The device can be used without any changes in conjunction with a CCD, both made on the basis of an n-type semiconductor and a p-type semiconductor. But in a device designed primarily for r-CCD operation on a p-type semiconductor, it is advisable to change it in comparison with FIG. 1 conductor transistors and bus power supplies to reverse.

Any transistor can be made according to the composite transistor circuit (Darlington circuit). This provides a higher energy efficiency of the device, especially in a predominantly static mode of its operation.

When mass production of the device, it is advisable to manufacture the elements of its circuit on one common crystal or on a small number of semiconductor crystals. In this case, in the device, instead of resistors, you can apply field-effect transistors with an insulated gate. MIS capacitors or capacitances of closed pn junctions can be used as capacitors.

The device works as follows.

The rectangular-shaped impulse voltage (Fig. 4, axis A) is fed from the output of the digital microcircuit to the input of the device and, acting on the current-limiting link (resistor 2 and capacitor 3), turns on the transistor 1 at time t This pulse voltage also flows through the capacitor 12 to the bases of the transistor 11 and is differentiated. Therefore, a negative exponentially falling impulse (Fig. 4, axis B, curve a) is formed on the basis of an pnp transistor 11, which closes this transistor at time t for its duration t at time t. Promeu-day time t; is determined by the time when this pulse exceeds the threshold voltage of the base Up of transistor 11. When transistor 1 is turned on simultaneously and transistor 11 is turned off, their collectors at time tj accept the potential close to the potential of the positive power supply bus E (Fig. 4, axis c ). The positive voltage drop arising on the collectors of these transistors is close in magnitude to the voltage of the second and third power sources (B2 + E). This voltage jump goes through two current-limiting stars (resistors 7 and 8 and capacitors 9 and 10) to the bases of an pnp transistor 4 and a ppn transistor 5, the transistor 4 being turned on and the transistor 5 off. Due to the high frequency of the device's transistors, as well as due to the existence of accelerating capacitors 9 and 10 in the current-limiting links, the switching of transistors 4 and 5 occurs almost immediately at time t. Thus, at this point in time, the collectors of transistors 4 and 5 abruptly acquire a potential close to the potential of the negative power supply bus E, (Fig. 4, d axis), which is reproduced at. using the output stage at the output of the device (Fig. 4, axis D). The negative voltage drop formed at time t on collectors of transistors 4 and 5, through the feedback resistor 6, acts on the base of transistor 11 (Fig. 4, axis B, curve b) and, decaying exponentially, confirms with some delay T by time off of this transistor. The time interval t is determined relative to the threshold voltage 5 NIN Up at the base of the transistor 11. The magnitude of the resistor b and the capacitor 12 is chosen so that the value C is less than T. In time, t potential input

jj jumps to level 1 and closes transistor 1. At the base of transistor 11, this positive voltage jump corresponds to an exponential sync pulse (Fig. 4,

- axis B, curve c), which opens

 the transistor 11 at time t. At this moment in time, the collectors of transistors 1 and 11 form a negative voltage drop (Fig. 4, axis c), which through current-limiting links affects the bases of transistors 4 and 5. Therefore, transistor 4 closes and transistor 5 opens, i.e. the potential of the collectors of these transistors at the moment of shortening to a jump acquires a potential close to the potential of the positive power supply line of the source I E (Fig. 4, d axis). This level is reproduced at the output of the device.

Q (Fig. 5, axis D) using the output stage. A positive voltage surge through feedback resistor 6 confirms the on state of the transistor 11 with some delay tj (Fig. 4, axis

B, curve d), but until termination of the differentiated input voltage differential (Fig. 4, B axis, curve c). Output level maintained until time

0 3 when the next period of operation of the device begins.

In the proposed device, the reduction of energy consumed is achieved mainly due to almost

5 completely eliminating the static value of the current of the input transistor; when using the proposed device in a television set and in ny chambers close to the frequency of decomposition, the broadcast standard, the total energy savings of the power source (taking into account both the continuous pulse shaping mode and the static mode of operation) will be at least 30%.

Claims (2)

1. A pulse shaping device containing an input transistor, the base of which is connected to the input signal bus through a current-limiting circuit consisting of a parallel-connected resistor and a capacitor, two switching transistors of different types of conductivity, the emitters of which are connected to the positive and negative buses of the first power source, the collectors are connected to one output of the feedback resistor, and the bases are connected via similar current-limiting links to the collector of the input transistor, I distinguish EEC in that, to reduce the absorbed power and increasing the repetition frequency of the pulses generated, the additional introduced into it an inverse transistor with respect to the input transistor of the conduction type, an additional capacitor and an output stage, the auxiliary transistor collector is connected to the input transistor collector, an emitter connected to the second power supply bus, the emitter of the additional transistor is connected to the third power supply bus, and the base is connected directly to another the output of the feedback resistor and connected through an additional capacitor to the bus input signals, while the collectors are switching a transistor connected to the bus output signals through the output stage. 2. The device according to claim 1, characterized in that the output stage contains two transistors of different conductivity type, the emitters of which are connected to the power supply buses, the bases through current limiting links connected to the input, and the collectors to the output bus of the cascade Sources of information taken into account in the examination 1.Budinsky J. Logic circuits in digital technology. M., Holy Hour, 1977, p. 337. 2. US patent number 3858059, class. 307264, 1974 (prototype). one. xFig. 2