SU1462500A1 - Device for identifying clocking pulses - Google Patents

Abstract

The invention relates to television technology. The purpose of the invention is to improve the noise immunity and accuracy of detection of sync-bottom pulses. The device contains a selector of 1 pulses of a positive POLAR110 (TI, counters 2 and 9 pulses, a block for selecting 3 frame sync pulses, elites AND 4, 5, 6 and 10, a single-vibrator 7 and el-IT I-8. stability is achieved by setting the boundary values of the number of pulses in a full sync signal, and the detection accuracy is achieved by controlling the duration of grlnich1,1x pulses. 1 Il.

Description

1U

The invention relates to television technology, in particular, to devices (Identification of clock signals.

The purpose of the invention is to increase the noise immunity and accuracy of detecting the sync signals.

The drawing shows the functional diagram of the device.

; The device contains a selector 1 sync pulses of positive polarity, a counter of 2 pulses, a block of 3 p1 and personnel sync pulses, elements AND 4-6, a single vibrator 7, an element AND-HE 8, a counter 9 pulses and element And .10.

When a presence of a full-television signal of positive polarity is detected on its own: the device produces a pulse on; 1 going The device is intended for use in interface circuits of a VCR with a television receiver.

I The device works as follows.

I Upon receipt of a positive signal at the input of the television signal. Field of choice selector 1 forms on its full sync signal, including frame and line synchronization pulses. As the selector P1 |), there is a standard pattern for allocating the synchronization pulses of a television receiver. Block 3 also removes the framing signal from this signal. synchronization, each of which resets the counter 2.

: After the termination of the frame sync and pulse at the reset inputs R and the counting of counter 2, there are l left logical levels, therefore, the cr | 1 detector starts counting the pulses from the output of the selector 1 to input V. When the counter 2 is counted 288 pulses from the moment of termination of the frame sync pulse are outputted to the output D (element 5, a signal is received with a voltage of 1. (inputs of the element 5 are subconnect C1 (outputs to the sixth and ten decals) of counter 2). This signal is saved to the arrival of the next frame clock, since the number of pulses , is -, in a full synchronization signal m (waiting for two frame sync pulses, taking into account the balancing, should not exceed 320. In this case, the next frame sync pulse again

resets counter 2, and a short pulse is generated at the output of element And 6, the duration of which is approximately equal to the value of the delay for resetting counter 2 .and switching element And 5.

If before the arrival of the next personnel sync pulse counter 2 counts to 320, the element 5 will close, and the element 4 will open and prevent the operation of the counter 2 at the C input.

During normal operation, i.e. when a frame sync pulse arrives before the element 4 triggers, a pulse from the output of element 6 starts the one-shot 7, the pulse duration of which is close to the pulse duration at the output of block 3, but somewhat less. The signal from the output of the single-oscillator 7 opens the element AND-HE 8, as a result of which the reset signal on the R input of counter 9 ceases to act, and it counts the pulses acting on input V.

During the action of the frame sync pulse from the selector 1 selector, there are impulses of tie-in with a double line frequency. After the fourth pulse arrives, a third logical level appears at the output of the third bit of counter 9, which persists until the end of the pulse at the output of the single-oscillator, since the number of tie-in pulses fed to the counting input of counter 9 during the pulse of the single-oscillator 7 should not be less than four, but no more than eight (after counting by eight. pulses at the output of the third bit of counter 9 is set to zero, and at the output of the fourth bit a single logic level. The last one stops the counter in this position, before a single logical level arrives on its Cgvhod.

After the end of the pulse at the output of the one-shot 7, the element AND-HE 8- is closed, the counter 9 is zeroed, and at the output of the element 10 a pulse occurs with level 1, the duration of which is determined by the delay time for resetting the counter 9 and switching the element AND-HE 8 .

Thus, pulses on the upper level of the And 10 element appear periodically when three conditions are met that correspond to the input of a full telepision signal of positive polarity to the device input:

1) the number of pulses at the output, the selector 2, arising between two frame sync pulses, ranges from 288 to 319;

2) the number of pulses at the output of the selector 1 during the action of the pulse at the output of the one-shot 7 is in the range from 4 to 7 m;

3) the duration of the pulses at the output of the block allocation frame HRs is longer than the duration of the pulses at the output of the one-shot.

Thus, the proposed device in comparison with the device prototype provides a higher noise immunity due to

pulse selector of positive polarity, HR sync pulse allocation unit, first and second additional elements AND, NAND element and second pulse counter, the first output of which is connected to the enable input of the second counter, and the second output of the counter is connected to the second

fO by the input of the second element I, the counting input of the second counter is combined with the counting input of the first pulse counter and connected to the output of the selector pulse of positive polarity

15 and with the input of the block of sync pulse frames, the output of which is connected to the zeroing input of the first pulse counter, the first input of the NAND element and the first input of the first element

setting the boundary values of the number 20 whose output is connected to the input

pulses in a full sync signal and increased detection accuracy by controlling the duration of boundary pulses.

one-shot, a-to the second input of the first element And the output of the first additional element I is connected, the input of which is connected respectively to the first and second outputs of the first pulse counter, the permitting input of which is connected to the output of the second additional element And whose inputs are connected respectively to the first and third exits first. a pulse counter, the output of the element IS-NOT is connected to the zero input of the second pulse counter, the second input of the element IE is connected to the 2g direct output of the one-shot, and

Claims (1)

Invention Formula A synchronization pulse detection device containing the first pulse counter, the first And element and the one-shot, the inverse output of which is connected to the first input of the second And element, the output of which is the output of the device, characterized in that, in order to increase the noise immunity and accuracy of the pulses sync entered into it 1462500 positive polarity pulse selector, frame sync pulse allocation unit, first and second AND additional elements, AND-NOT element and second pulse counter, the first output of which is connected to the second counter enabling input, and the second counter output is connected to the second the input of the second element And, the counting input of the second counter is combined with the counting input of the first pulse counter and is connected to the output of the pulse selector of positive polarity and with the input of the block of personnel sync pulses, the output of which is connected to the zeroing input of the first pulse counter, the first input of the NAND element and the first input of the first element  the output of which is connected to the input one-shot, a to the second input of the first element And connected to the output of the first additional element And, the inputs of which are connected respectively to the first and second outputs of the first pulse counter, allowing the input of which is connected to the output of the second additional element And, the inputs of which are connected respectively to the first and third outputs the first pulse counter, the output of the NAND element is connected to the zeroing input of the second pulse counter, the second input of the NIP element is connected to the g direct output of the one-vibrator, and the input of the pulse vector put positive (. the polarity is the input of the device). five 0