SU1383472A1 - Time pulse discriminator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in systems for receiving, processing and transmitting information. The invention makes it possible to increase the reliability of the device by simplifying it. For this, the first 6 and second 7 BAN elements are additionally entered into the device. In addition, the device contains the element RSHI 1, the element I 2, the first input bus 3, the second bus 4. and the second input bus 5. The BAN element is performed on one transistor and two resistors. When the tires 3 and 5 pulses come at different times, then. there is no pulse on the output pin 4, which ensures an appropriate time selection of pulses. The operation of the device is explained in the time diagrams provided in the description of the invention. 3 il.

Description

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The invention relates to a pulse technique and can be used in reception systems, processing and transmission of information,

The purpose of the invention is to increase the reliability of the device by simplifying it.

Fig. 1 shows a structural electrical circuit of the device; on q 1 fig 2 — the BAN element in FIG. 3 - time diagrams, which explain the operation of the device, | a) on the first input bus, b) on the | second input bus, c) on the output 5 bus.

The device (FIG. 1) contains the element OR 1, the first, whose input is connected to the output of the element 2, the first input of which is connected to the first input bus 3 and the output to the output bus 4. The first and second input | buses 3 and 5 are connected respectively | to the direct inputs of the first and second elements BANCH 6 and 7, the inverse 25 inputs of which are connected to the outputs of the BANNER elements 7 and 6, respectively. The output of the ZAGSRET element 7 is connected to the second input of the element OR 1, the output of which is connected to the second input of the element AND 2,

The BANNER element (FNG.2) contains the first resistor 8, the first output of which is connected to the direct input of the element, and the second output is connected to the output of the element and to the collector of transistor 9, the emitter of which is connected to the common bus of the device, and the base - through the second resistor 10 with inverse element input.

13834722

At the same time, the pulse from the bus 4 is fed to the first input of the element OR 1.

time tj pulse on the bus

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5 is terminated, but logical 1 at the output of element 1 continues to be present as long as there is a high potential on tires 3 and 4. B is a moment in time t. the pulse ends on the tires 3 and 4 and the selector returns to the initial state. Thus, despite the fact that there is only a partial coincidence in time of the pulses from tires 3 and 5, a pulse arriving on bus 3 is formed on bus 4 without distorting its duration, provided that the leading edge of the pulse on bus 5 arrives earlier than the front pulse front on bus 3. If the leading edge of a pulse on a tweezer 3 comes before the leading front on bus 5, the output pulse on bus 4 does not form, since at the time T of the pulse on bus 3, the output level of element 6 forms a logical 1 and when the pulse arrives on the bus 5 at the time T at the output of element 7 and the second input of the element OR 1, the logic level 1 is not formed, i.e. pulses on bus 3, leading pulses on bus 5 to bus 4, do not pass.

Claims (3)

Invention Formula A temporary pulse selector containing the AND element, the first input of which is connected to the first input bus, the second input to the output of the OR element, and the output to the first input of the OR element, as well as the second input bus and output bus, which is - Sch and with the fact that, in order to increase the reliability of the selector due to its simplification, the first and second elements of the BANGE are entered into it, the direct inputs of which are connected respectively with the first and second input buses, the inverse inputs with the outputs of the second and the first element BAN, and the output of the second lementa BAN is connected to the second input of the OR gate, the output of AND element is connected to the output bus. The device works as follows. If the pulses on pin 3 and 5 are on; at one time or another, then there is no pulse on the output bus 4. At the moment of time tf, a pulse arrives at the bus 5 (FIG. 26), and at the output of element 7 a high potential is formed, which through the element OR 1 enters the second input of the element AND 2. In the moment: t of time t, a pulse arrives on the bus 3 (Fig. 2a) and on the bus 4 (Fig. 2c) the leading edge of the output pulse is formed, d 5 0 5 o time tj pulse on the bus five 0 five 0 AT 5 is terminated, but logical 1 at the output of element 1 continues to be present as long as there is a high potential on tires 3 and 4. B is a moment in time t. the pulse ends on the tires 3 and 4 and the selector returns to the initial state. Thus, despite the fact that there is only a partial coincidence in time of the pulses from tires 3 and 5, a pulse arriving on bus 3 is formed on bus 4 without distorting its duration, provided that the leading edge of the pulse on bus 5 arrives earlier pulse front on bus 3. If the leading edge of the pulse on tweez 3 comes before the leading edge on bus 5, the formation of the output pulse on bus 4 does not occur, since at the time T of the arrival of the pulse on bus 3, the output level of element 6 forms a logical level 1 and upon arrival pulse to bus 5 at time T at the output of element 7 and the second input of the element OR 1, the logical level 1 is not formed, i.e. pulses on bus 3, leading pulses on bus 5 to bus 4, do not pass. Invention Formula A temporary pulse selector containing the AND element, the first input of which is connected to the first input bus, the second input to the output of the OR element, and the output to the first input of the OR element, as well as the second input bus and output bus, which is - Sch and with the fact that, in order to increase the reliability of the selector due to its simplification, the first and second elements of the BANGE are entered into it, the direct inputs of which are connected respectively with the first and second input buses, the inverse inputs with the outputs of the second and the first element BAN, and the output of the second lementa BAN is connected to the second input of the OR gate, the output of AND element is connected to the output bus. i  "I 9g.Z