JPH0481074U - - Google Patents
Info
- Publication number
- JPH0481074U JPH0481074U JP12429290U JP12429290U JPH0481074U JP H0481074 U JPH0481074 U JP H0481074U JP 12429290 U JP12429290 U JP 12429290U JP 12429290 U JP12429290 U JP 12429290U JP H0481074 U JPH0481074 U JP H0481074U
- Authority
- JP
- Japan
- Prior art keywords
- input signal
- level
- counting
- absolute value
- threshold level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
第１図は本考案の一実施例によるピーク値検出
回路のブロツク図、第２図は従来のピーク値検出
回路の回路図、第３図は本考案のピーク値検出回
路の動作を説明するための図である。
１は入力端子、２は出力端子、３はダイオード
、４はコンデンサ、５は抵抗器、６はコンパレー
タ、７はコンパレータ、８はカウンター、９はカ
ウンター、１０は演算回路。
Fig. 1 is a block diagram of a peak value detection circuit according to an embodiment of the present invention, Fig. 2 is a circuit diagram of a conventional peak value detection circuit, and Fig. 3 is for explaining the operation of the peak value detection circuit of the present invention. This is a diagram. 1 is an input terminal, 2 is an output terminal, 3 is a diode, 4 is a capacitor, 5 is a resistor, 6 is a comparator, 7 is a comparator, 8 is a counter, 9 is a counter, and 10 is an arithmetic circuit.
Claims (1)
ドレベルに比較する比較手段と、前記入力信号の
絶対値のレベルを前記スレツシユホールドレベル
を越えた回数を計数する第１の計数手段と、前記
入力信号の絶対値のレベルが前記スレツシユホー
ルドレベルを越えている時間幅の総計を計数する
第２の計数手段と、前記第２の計数手段の計数値
を前記第１の計数手段の計数値で割り算し、前記
入力信号の絶対値のレベルが前記スレツシユホー
ルドレベルを越えた回数の時間平均を出力すると
共に、該時間平均を基に前記入力信号のピーク値
を演算する演算手段とを有することを特徴とする
ピーク値検出回路。 a comparing means for comparing the absolute value level of the input signal with a threshold level; a first counting means for counting the number of times the absolute value level of the input signal exceeds the threshold level; and the input signal a second counting means for counting the total time period during which the level of the absolute value of exceeds the threshold level; and dividing the count value of the second counting means by the count value of the first counting means. and calculating means for outputting a time average of the number of times the absolute value level of the input signal exceeds the threshold level, and calculating a peak value of the input signal based on the time average. Features a peak value detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12429290U JP2545246Y2 (en) | 1990-11-28 | 1990-11-28 | Peak value detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12429290U JP2545246Y2 (en) | 1990-11-28 | 1990-11-28 | Peak value detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0481074U true JPH0481074U (en) | 1992-07-15 |
| JP2545246Y2 JP2545246Y2 (en) | 1997-08-25 |
Family
ID=31871951
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12429290U Expired - Lifetime JP2545246Y2 (en) | 1990-11-28 | 1990-11-28 | Peak value detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2545246Y2 (en) |
-
1990
- 1990-11-28 JP JP12429290U patent/JP2545246Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2545246Y2 (en) | 1997-08-25 |
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