JPH0478571U - - Google Patents
Info
- Publication number
- JPH0478571U JPH0478571U JP12090390U JP12090390U JPH0478571U JP H0478571 U JPH0478571 U JP H0478571U JP 12090390 U JP12090390 U JP 12090390U JP 12090390 U JP12090390 U JP 12090390U JP H0478571 U JPH0478571 U JP H0478571U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- comparison
- time
- peak
- peak voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 13
- 102100029469 WD repeat and HMG-box DNA-binding protein 1 Human genes 0.000 description 1
- 101710097421 WD repeat and HMG-box DNA-binding protein 1 Proteins 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
第１図は本考案の一実施例を示すブロツク図で
ある。
１……ピーク電圧検出部、２……経過時間検出
部、３……ピーク電圧検出開始信号、４……被検
出電圧、５……比較結果信号、６……ゲート信号
、７……比較電圧、８……比較電圧発生用計数回
路、９……比較電圧データ信号、１０……計数ク
ロツク発生回路、１１……計数クロツク信号、１
２……比較電圧データ保持回路、１３……ピーク
電圧データ信号、１４……経過時間計数回路、１
５……経過時間計数データ信号、１６……経過時
間計数データ保持回路、１７……経過時間データ
信号、ＡＮＤ１，ＡＮＤ２……ＡＤＮゲート、Ｃ
１……電圧比較器、ＤＡ……Ｄ−Ａ変換器。
FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Peak voltage detection section, 2... Elapsed time detection section, 3... Peak voltage detection start signal, 4... Voltage to be detected, 5... Comparison result signal, 6... Gate signal, 7... Comparison voltage , 8...Counting circuit for generating comparison voltage, 9...Comparison voltage data signal, 10...Counting clock generation circuit, 11...Counting clock signal, 1
2... Comparison voltage data holding circuit, 13... Peak voltage data signal, 14... Elapsed time counting circuit, 1
5...Elapsed time count data signal, 16...Elapsed time count data holding circuit, 17...Elapsed time data signal, AND1, AND2...ADN gate, C
1... Voltage comparator, DA... DA converter.
Claims (1)
出開始信号とを入力し、所定のクロツク信号を基
準として比較電圧の値をあらかじめ定められた間
隔で変化させて前記被検出電圧の値と比較し、前
記比較電圧がピーク電圧に達した時点の比較電圧
をピーク電圧として出力するピーク電圧検出手段
と、前記検出開始信号を入力して前記クロツク信
号を基準として時間の計数を継続し前記比較電圧
がピーク電圧に達した時点の制御信号により継続
した時間計数を保持して出力する経過時間検出手
段とを有することを特徴とするピーク電圧検出回
路。 ２ 前記ピーク電圧検出手段が前記クロツク信号
の周期にしたがつて電圧を所定の傾斜で増大させ
て行く比較電圧を発生する比較電圧発生回路と、
前記比較電圧と前記被検出電圧を入力し、前記比
較電圧が前記被検出電圧より大きくなつた時点で
反転信号を出力する比較判定回路と、前記反転信
号を入力してその時点の前記比較電圧を記憶する
電圧データ保持回路とを有することを特徴とする
請求項１記載のピーク電圧検出回路。 ３ 前記経過時間検出手段が前記クロツク信号と
前記検出開始信号とを入力し時間計数を行う計数
回路と、前記ピーク電圧検出手段から入力される
反転信号により前記計数回路で計数された値を記
憶する時間データ保持回路とを有することを特徴
とする請求項１および２記載のピーク電圧検出回
路。[Claims for Utility Model Registration] 1. A voltage to be detected having a peak voltage and a detection start signal are input from the outside, and the value of the comparison voltage is changed at predetermined intervals using a predetermined clock signal as a reference to detect the detected voltage. peak voltage detection means that compares the value of the detected voltage and outputs the comparison voltage at the time when the comparison voltage reaches the peak voltage as a peak voltage; and inputs the detection start signal and counts time using the clock signal as a reference. and elapsed time detection means for holding and outputting a continuous time count based on a control signal at the time when the comparison voltage reaches a peak voltage. 2. A comparison voltage generation circuit in which the peak voltage detection means generates a comparison voltage whose voltage increases at a predetermined slope according to the period of the clock signal;
a comparison judgment circuit that inputs the comparison voltage and the detected voltage and outputs an inverted signal when the compared voltage becomes larger than the detected voltage; 2. The peak voltage detection circuit according to claim 1, further comprising a voltage data holding circuit for storing voltage data. 3. The elapsed time detection means inputs the clock signal and the detection start signal to a counting circuit that counts time, and stores the value counted by the counting circuit based on an inverted signal input from the peak voltage detection means. 3. The peak voltage detection circuit according to claim 1, further comprising a time data holding circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12090390U JPH0478571U (en) | 1990-11-19 | 1990-11-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12090390U JPH0478571U (en) | 1990-11-19 | 1990-11-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0478571U true JPH0478571U (en) | 1992-07-08 |
Family
ID=31868785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12090390U Pending JPH0478571U (en) | 1990-11-19 | 1990-11-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0478571U (en) |
-
1990
- 1990-11-19 JP JP12090390U patent/JPH0478571U/ja active Pending
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