JPH0390134U - - Google Patents
Info
- Publication number
- JPH0390134U JPH0390134U JP14858089U JP14858089U JPH0390134U JP H0390134 U JPH0390134 U JP H0390134U JP 14858089 U JP14858089 U JP 14858089U JP 14858089 U JP14858089 U JP 14858089U JP H0390134 U JPH0390134 U JP H0390134U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- digital value
- pulse width
- width modulation
- preset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000465 moulding Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Inverter Devices (AREA)
- Control Of Ac Motors In General (AREA)
Description
第１図は本考案のパルス幅変調装置の一実施例
を示すブロツク図、第２図ａ，ｂは第１図に示す
実施例の内容を示すタイムチヤート、第３図はパ
ルス幅変調装置の従来例を示すブロツク図、第４
図ａ，ｂ，ｃ，ｄは第３図に示す従来例の中の各
信号を示す波形図である。
１……プリセツト制御部、１１，１２……記憶
部、２，３……プリセツトカウンタ、ＤＮ１……
第１のデイジタル値、ＤＮ２……第２のデイジタ
ル値、ＰＳ……プリセツト信号、ΦＷ……減算ク
ロツク、ＬＳ……ラツチ信号。
FIG. 1 is a block diagram showing an embodiment of the pulse width modulation device of the present invention, FIGS. 2a and b are time charts showing the details of the embodiment shown in FIG. 1, and FIG. Block diagram showing a conventional example, No. 4
Figures a, b, c, and d are waveform diagrams showing each signal in the conventional example shown in FIG. 3. 1... Preset control unit, 1 1 , 1 2 ... Storage unit, 2, 3... Preset counter, DN1...
First digital value, DN2...second digital value, PS...preset signal, ΦW...subtraction clock, LS...latch signal.
Claims (1)
て第１の信号ＶＰ１を出力する時間を規定しうる
第１のプリセツトカウンタ２と、与えられる第２
のデイジタル値ＤＮ２によつて第２の信号ＶＰ２
を出力する時間を規定しうるとともに、第１の信
号ＶＰ１の出力の終了をまつて出力を開始する第
２のプリセツトカウンタ３と、 あらかじめ記憶している第１および第２のデイ
ジタル値ＤＮ１，ＤＮ２を所定の時間毎にそれぞ
れ第１および第２のプリセツトカウンタ２，３に
与えるプリセツト制御部１とを有することを特徴
とするパルス幅変調装置。 ２ 成形機を作動させるパルス幅変調インバータ
のトリガ回路として用いられる請求項１記載のパ
ルス幅変調装置。[Claims for Utility Model Registration] 1. A first preset counter 2 capable of defining the time for outputting a first signal VP1 based on a given first digital value DN1, and a given second digital value DN1.
The second signal VP2 is determined by the digital value DN2 of
a second preset counter 3 which can define the time for outputting the signal VP1 and which starts outputting after the end of the output of the first signal VP1; and a pre-stored first and second digital value DN1, 1. A pulse width modulation device comprising a preset control section 1 for applying DN2 to first and second preset counters 2 and 3, respectively, at predetermined time intervals. 2. The pulse width modulation device according to claim 1, which is used as a trigger circuit for a pulse width modulation inverter that operates a molding machine.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14858089U JPH0390134U (en) | 1989-12-26 | 1989-12-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14858089U JPH0390134U (en) | 1989-12-26 | 1989-12-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0390134U true JPH0390134U (en) | 1991-09-13 |
Family
ID=31695023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14858089U Pending JPH0390134U (en) | 1989-12-26 | 1989-12-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0390134U (en) |
-
1989
- 1989-12-26 JP JP14858089U patent/JPH0390134U/ja active Pending