JPS6232641U - - Google Patents
Info
- Publication number
- JPS6232641U JPS6232641U JP12527185U JP12527185U JPS6232641U JP S6232641 U JPS6232641 U JP S6232641U JP 12527185 U JP12527185 U JP 12527185U JP 12527185 U JP12527185 U JP 12527185U JP S6232641 U JPS6232641 U JP S6232641U
- Authority
- JP
- Japan
- Prior art keywords
- counter
- stage
- counters
- value
- input data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図はこの考案の一実施例を示すブロツク図
、第２図は第１図の装置の動作を示す動作タイム
図、第３図は従来の装置を示すブロツク図。
１は入力端子、２は出力端子、３は判定装置、
６０はレジスタ、６１〜６６はそれぞれカウンタ
。尚、各図中同一符号は同一又は相当部分を示す
。
FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2 is an operation time diagram showing the operation of the device shown in FIG. 1, and FIG. 3 is a block diagram showing a conventional device. 1 is an input terminal, 2 is an output terminal, 3 is a determination device,
60 is a register, and 61 to 66 are counters. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
設計によつて定める正の整数）その計数値の出力
を縦続的に接続して、前段のカウンタの計数値を
後続段のカウンタのプリセツト値として入力する
ようにし、最前段のカウンタのプリセツト値は数
値０とするように構成したカウンタ群、 計数の対象となる入力データを上記カウンタ群
の各カウンタに並列に入力する手段、 上記入力データが論理「１」のときはその都度
、上記各カウンタの計数値を１だけ増加し、上記
入力データが論理「０」のときはその部度、上記
各カウンタの計数値を後続するカウンタにプリセ
ツトし最前段のカウンタには数値０をプリセツト
する手段、 最後段のカウンタの計数値を設計により定めた
数値と比較する判定装置を備えた計数装置。[Claims for Utility Model Registration] m presettable pulse counters (m is a positive integer determined by the design) are connected in series, and the outputs of the counters in the previous stage are used as the counters in the subsequent stage. a counter group configured such that the preset value of the counter at the front stage is inputted as a preset value of the counter, and the preset value of the counter at the frontmost stage is a numerical value of 0; means for inputting input data to be counted in parallel to each counter of the counter group; , Each time the above input data is a logic "1", the count value of each of the above counters is increased by 1, and when the above input data is a logic "0", the count value of each of the above counters is increased by 1. A counting device comprising a means for presetting a counter at the last stage and a numerical value 0 for the counter at the first stage, and a determination device for comparing the counted value of the last stage counter with a numerical value determined by design.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12527185U JPS6232641U (en) | 1985-08-14 | 1985-08-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12527185U JPS6232641U (en) | 1985-08-14 | 1985-08-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6232641U true JPS6232641U (en) | 1987-02-26 |
Family
ID=31018025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12527185U Pending JPS6232641U (en) | 1985-08-14 | 1985-08-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6232641U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0216209U (en) * | 1988-07-18 | 1990-02-01 |
-
1985
- 1985-08-14 JP JP12527185U patent/JPS6232641U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0216209U (en) * | 1988-07-18 | 1990-02-01 |
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