JPS5840946U - random pulse counter - Google Patents

random pulse counter

Info

Publication number
JPS5840946U
JPS5840946U JP13511881U JP13511881U JPS5840946U JP S5840946 U JPS5840946 U JP S5840946U JP 13511881 U JP13511881 U JP 13511881U JP 13511881 U JP13511881 U JP 13511881U JP S5840946 U JPS5840946 U JP S5840946U
Authority
JP
Japan
Prior art keywords
pulses
random pulse
pulse counter
counter
random
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13511881U
Other languages
Japanese (ja)
Inventor
上田 敏晴
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP13511881U priority Critical patent/JPS5840946U/en
Publication of JPS5840946U publication Critical patent/JPS5840946U/en
Pending legal-status Critical Current

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  • Measuring Frequencies, Analyzing Spectra (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図はこの発明の一実施例を示すブロック回路図・であり
、図中1はランダムパルスの入力端子、2はカウンタ、
3はカウンタの計数値を伝送する出力信号線、4はカウ
ンタ2−の表示値からべき数あるいはべき数によるカウ
ント数を求めるべき数構出回路、5はその出力信号線、
6はサンプリング時間発生回路、7はそのサンプリング
時間の伝送線、8はカウンタ2のゲート入力端子である
The figure is a block circuit diagram showing an embodiment of the present invention, in which 1 is a random pulse input terminal, 2 is a counter,
3 is an output signal line for transmitting the counted value of the counter, 4 is a number calculation circuit for calculating the exponent or the count number by the exponent from the display value of the counter 2-, 5 is its output signal line,
6 is a sampling time generating circuit, 7 is a transmission line for the sampling time, and 8 is a gate input terminal of the counter 2.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ランダムパルスの計数率を測定するカウンターに於いて
、前のサンプリング時間中にカウントしたパルス数のべ
き数によるパルス数を求め、このパルス数との積が一定
値となるべき数による時間をサンプリング時間とするこ
とによりランダムパルス計数率の統計偏差を自動的に一
定とならしめるランダムパルスカウンタ。
In a counter that measures the counting rate of random pulses, the number of pulses is determined by the power of the number of pulses counted during the previous sampling time, and the sampling time is determined by the number whose product with this number of pulses is a constant value. A random pulse counter that automatically makes the statistical deviation of the random pulse counting rate constant.
JP13511881U 1981-09-10 1981-09-10 random pulse counter Pending JPS5840946U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13511881U JPS5840946U (en) 1981-09-10 1981-09-10 random pulse counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13511881U JPS5840946U (en) 1981-09-10 1981-09-10 random pulse counter

Publications (1)

Publication Number Publication Date
JPS5840946U true JPS5840946U (en) 1983-03-17

Family

ID=29928501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13511881U Pending JPS5840946U (en) 1981-09-10 1981-09-10 random pulse counter

Country Status (1)

Country Link
JP (1) JPS5840946U (en)

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