JPS61179836U - - Google Patents
Info
- Publication number
- JPS61179836U JPS61179836U JP6349685U JP6349685U JPS61179836U JP S61179836 U JPS61179836 U JP S61179836U JP 6349685 U JP6349685 U JP 6349685U JP 6349685 U JP6349685 U JP 6349685U JP S61179836 U JPS61179836 U JP S61179836U
- Authority
- JP
- Japan
- Prior art keywords
- counter
- circuit
- output
- unit
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
Landscapes
- Emergency Protection Circuit Devices (AREA)
Description
第１図は本考案によるユニツトカウンタのカウ
ンタユニツトと他のユニツトを用いて多段設定す
る場合の接続状態を示す図、第２図はカウンタユ
ニツトの内部構成を示すブロツク図、第３図は複
数のカウンタユニツトを用いて繰り返し動作をさ
せる場合の接続図である。
Ａ―１〜Ａ―ｎ……カウンタユニツト、Ｂ……
入出力ユニツト、Ｃ―１〜Ｃ―ｎ……ＢＣＤ―１
０ビツト変換ユニツト、Ｄ―１〜Ｄ―ｎ……プリ
セツト出力ユニツト、Ｅ―１〜Ｅ―ｎ，Ｆ―１１
〜Ｆ―ｎｍ……データ設定器、Ｘ，Ｘ１，Ｘｍ…
…リレー、１……１０進カウンタ、２……一致検
出部、３……表示部、４……出力回路、５……ノ
ツト回路、６……アンド回路、７……Ｄ型フリツ
プフロツプ、８……ノア回路。
Fig. 1 is a diagram showing the connection state when the counter unit of the unit counter according to the present invention and other units are used for multi-stage setting, Fig. 2 is a block diagram showing the internal configuration of the counter unit, and Fig. FIG. 3 is a connection diagram when performing repeated operations using a counter unit. A-1 to A-n... Counter unit, B...
Input/output unit, C-1 to C-n...BCD-1
0 bit conversion unit, D-1 to D-n...Preset output unit, E-1 to E-n, F-11
~F-nm...Data setter, X, X1, Xm...
... Relay, 1 ... Decimal counter, 2 ... Coincidence detection section, 3 ... Display section, 4 ... Output circuit, 5 ... Not circuit, 6 ... AND circuit, 7 ... D-type flip-flop, 8 ... ...Noah circuit.
Claims (1)
式ユニツトカウンタであつて、 各カウンタユニツトは、入力信号を計数するカ
ウンタ回路、該カウンタ回路の計数を表示する表
示回路、該カウンタ回路の計数値を外部に出力す
る出力回路、該カウンタ回路及び表示回路を計数
中に強制リセツトするリセツト入力回路と、を有
し、 前記各カウンタユニツトの出力が与えられ設定
された計数データと一致するときに出力を出すデ
ータ設定器と、 前記データ設定器の一致出力の論理積に基づい
て出力を出すプリセツト出力ユニツトと、を具備
することを特徴とする電子式ユニツトカウンタ。 (2) 前記各カウンタユニツトのカウンタ回路は
、１桁の１０進カウンタであることを特徴とする
実用新案登録請求の範囲第１項記載の電子ユニツ
トカウンタ。 (3) 前記データ設定器はデジタルスイツチであ
ることを特徴とする実用新案登録請求の範囲第１
項記載の電子式ユニツトカウンタ。[Claims for Utility Model Registration] (1) An electronic unit counter to which a plurality of counter units are connected, each counter unit comprising a counter circuit that counts input signals and a display circuit that displays the count of the counter circuit. , an output circuit that outputs the counted value of the counter circuit to the outside, and a reset input circuit that forcibly resets the counter circuit and the display circuit during counting, and the output of each of the counter units is applied to the set count. 1. An electronic unit counter comprising: a data setter that outputs an output when it matches data; and a preset output unit that outputs an output based on a logical product of matching outputs of the data setter. (2) The electronic unit counter according to claim 1, wherein the counter circuit of each counter unit is a one-digit decimal counter. (3) Claim 1 of the utility model registration characterized in that the data setting device is a digital switch.
Electronic unit counter as described in section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6349685U JPS61179836U (en) | 1985-04-27 | 1985-04-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6349685U JPS61179836U (en) | 1985-04-27 | 1985-04-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61179836U true JPS61179836U (en) | 1986-11-10 |
Family
ID=30593699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6349685U Pending JPS61179836U (en) | 1985-04-27 | 1985-04-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61179836U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4888864A (en) * | 1972-02-23 | 1973-11-21 | ||
| JPS4893255A (en) * | 1972-03-10 | 1973-12-03 | ||
| JPS5338880A (en) * | 1976-09-22 | 1978-04-10 | Iwasaki Electric Co Ltd | Operating mode program control system |
-
1985
- 1985-04-27 JP JP6349685U patent/JPS61179836U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4888864A (en) * | 1972-02-23 | 1973-11-21 | ||
| JPS4893255A (en) * | 1972-03-10 | 1973-12-03 | ||
| JPS5338880A (en) * | 1976-09-22 | 1978-04-10 | Iwasaki Electric Co Ltd | Operating mode program control system |
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