JPS6320196U - - Google Patents

Info

Publication number
JPS6320196U
JPS6320196U JP11201986U JP11201986U JPS6320196U JP S6320196 U JPS6320196 U JP S6320196U JP 11201986 U JP11201986 U JP 11201986U JP 11201986 U JP11201986 U JP 11201986U JP S6320196 U JPS6320196 U JP S6320196U
Authority
JP
Japan
Prior art keywords
circuit
waveform
shaping circuit
vertical synchronization
synchronization signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11201986U
Other languages
Japanese (ja)
Other versions
JPH0438391Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11201986U priority Critical patent/JPH0438391Y2/ja
Publication of JPS6320196U publication Critical patent/JPS6320196U/ja
Application granted granted Critical
Publication of JPH0438391Y2 publication Critical patent/JPH0438391Y2/ja
Expired legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例を示すブロツク図
、第2図は第1図のブロツクの具体的回路図、第
3図は第2図の回路の各部信号波形図、第4図は
従来の垂直同期信号整型回路を示す図である。 22……波形整型回路、23……微分回路、2
4,25……トリガ検出回路。
Figure 1 is a block diagram showing an embodiment of this invention, Figure 2 is a specific circuit diagram of the block in Figure 1, Figure 3 is a signal waveform diagram of each part of the circuit in Figure 2, and Figure 4 is a conventional circuit. FIG. 2 is a diagram showing a vertical synchronization signal shaping circuit of FIG. 22...Waveform shaping circuit, 23...Differentiating circuit, 2
4, 25...Trigger detection circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力垂直同期信号と基準電圧とを比較し波形整
型する波形整型回路と、前記波形整型回路の出力
信号を微分する微分回路と、前記微分回路の微分
出力のトリガパルス部を検出するトリガ検出回路
とを具備したことを特徴とする垂直同期信号整型
回路。
a waveform shaping circuit that compares an input vertical synchronization signal with a reference voltage and shapes the waveform; a differentiating circuit that differentiates the output signal of the waveform shaping circuit; and a trigger that detects a trigger pulse portion of the differential output of the differentiating circuit. A vertical synchronization signal shaping circuit characterized by comprising a detection circuit.
JP11201986U 1986-07-23 1986-07-23 Expired JPH0438391Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11201986U JPH0438391Y2 (en) 1986-07-23 1986-07-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11201986U JPH0438391Y2 (en) 1986-07-23 1986-07-23

Publications (2)

Publication Number Publication Date
JPS6320196U true JPS6320196U (en) 1988-02-09
JPH0438391Y2 JPH0438391Y2 (en) 1992-09-08

Family

ID=30992494

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11201986U Expired JPH0438391Y2 (en) 1986-07-23 1986-07-23

Country Status (1)

Country Link
JP (1) JPH0438391Y2 (en)

Also Published As

Publication number Publication date
JPH0438391Y2 (en) 1992-09-08

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