JPS6037909B2 - electronic clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece that can be used as an additional function, such as a chronograph, as well as a hand movement type time display mechanism, if necessary.

When a hand movement type watch that uses a pulse motor as a converter is configured so that it can be used as an additional function such as a chronograph as needed, after performing timekeeping operations unrelated to standard time, Even if the clock operation is restored, the time display means loses track of the correct time due to the clock operation, so a troublesome time adjustment operation is required. An object of the present invention is to have a function of storing the time during which the additional function was in operation, and correcting the displayed time based on this memory when returning to normal watch operation after the additional function has finished operating. It is an object of the present invention to provide an electronic timepiece that can simplify a user's operations required to accurately display time.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An electronic timepiece with a chronograph function, which is an embodiment of the present invention, will be described with reference to the drawings. The electronic timepiece of this embodiment is assumed to have a hand movement type display mechanism having a second hand, a minute hand, and an hour hand. In the figure, reference numeral 1 denotes a reference signal oscillator that uses the frequency of a crystal oscillator as a time reference, and its oscillation output (frequency 327 old z as an example) is frequency-divided by a divider 2. This frequency divider 2 creates three types of signals from the reference signal, each having a frequency of 1st and 3rd, respectively.
c. Further, the fourth signal (frequency 64 ratio) obtained from the frequency divider 2 is supplied to waveform shaping circuits 3a, 3b, and 3c, respectively, and the IHz clock signal 1, 2Hz signal J2 and 3 (each 1/64 second during the pulse) is extracted with a 32 Hz signal. Among these signals, the IHz signal ◇1 is supplied to the drive circuit 6 for driving the pulse motor PM through the AND gate 4 and the OR gate 5, thereby causing the second hand to rotate by 1/6 every second. It rotates side by side and displays the time.

Further, a switch SM is provided which is closed at every positive second (when the second hand passes the 1st position). In addition, a flip-flop circuit (hereinafter referred to as "FF circuit") FFI and a changeover switch SI constitute operation switching means for switching between normal clock operation and additional function operation, and a changeover switch SI
When the clock is operating (when the switching switch SI is OFF), the logic of the output QI is "0" and the logic of the output QI is "1" when the clock is operating (when the switching switch SI is ON).
is configured to be inverted.

Furthermore, when the logic of the output QI of the FF circuit 1 becomes "1", a reset pulse Rp is taken out via the differentiating circuit 7. And the FF circuit FF set by the output 91
The output Q3 of 3 takes the logic "1" when the logic of the output QI is "IJ" and opens the AND gate 4. During normal clock operation, A is opened by the output Q3 of the FF circuit FF3.
Via the ND gate 4, the IHz signal ◇1 is sent to the drive circuit 6, which causes the pulse motor PM to advance the second hand.

However, when the switching switch SI is turned on to obtain a timekeeping operation, the logic of the output QI of the FF circuit FFI becomes "1", so the logic of the output Q3 of the FF circuit FF3 becomes "OJ", and the AND gate 4 The gate of is closed and the signal 1 is no longer sent to the drive circuit 6.

In other words, normal clock operation stops. Furthermore, when the logic of the output QI becomes "1", the gate of the AND circuit 9 is opened,
The output ◇3a is supplied to one input terminal of the AND gate 11 of the return circuit 10. This AND gate 11 is connected to the FF circuit F set by the reset pulse Rp.
While opened by the output Q4 of F4, the return signal G3
a is allowed to be sent to the drive circuit 6 via the OR circuit 5, and therefore the pulse motor PM rapidly rotates with a pulse of 32& to rapidly advance the second hand. When the second hand reaches the 1st position, the switch SM is turned on and the FF circuit FF4 is set to 1' via the differentiating circuit 12, and the second hand stops at that position, completing the dropping operation. . Note that a similar return-to-zero operation can also be performed by manually turning on the switch S2 and sending a set pulse to the FF circuit FF4 via the differentiating circuit 13. - Timekeeping circuit 14 for obtaining timekeeping operation that can be used as a stopwatch
is temporarily turned ON at the start and end points of timekeeping by the user.
The timer switch S3 is turned on only once by the user, which has a timer switch S3 that is turned on, a differentiator circuit 15 that generates a pulse for each operation, and a T-type FF circuit FF5 that inverts the output state with respect to this pulse. , the logic of the output Q5 of the FF circuit FF5 changes from "0-1" to "1", and the gate of the AND gate 16 opens.

This allows AND gate 17 (which gate has output Q
The 2Hz signal ◇2a from the output side of the AND gate 16 gives a clock signal ◇2b to the output side of the AND gate 16, and this signal ◇2b is supplied to the drive circuit 6 so that the second hand moves two steps every second. (2/60 revolutions) at a time. That is, in this case, operation as a chronograph having a timekeeping hand of 1 rotation and 3 currents can be obtained. Also, the timing switch S3
When the FF circuit FF5 turns ON for the second time, the logic of its output 5 becomes OJ and closes the AND gate 16, so the second hand stops advancing immediately.In this state, the zero switch is turned on. If you press S2, the second hand will quickly start zeroing due to the operation described above, so by performing this operation in an appropriate order, you can obtain the stopwatch function.Also, only while the output Q3 of the FF circuit FF3 is ON. A
Open the ND gate 18, pass through this AND gate 18,
The signal ◇1 is supplied to the down-counting input terminal of the up/down counter 19. This counter 19 is a clock signal storage circuit that stores 1 in the clock signal generated during the operation of the additional function, and stores the clock signal ? 2b and zero return signal 3b
is used as an input for up-counting, and the clock signal CI is used as an input for down-counting, and the signal operates to count down the number of pulses of 1 from the time immediately after being reset by the reset pulse Rp. On the other hand, as mentioned above, the OR gate 20 is connected to the up-counting input terminal of the counter 19.
and three types of signals 2b, 0 through the AND gate 21.
3b and 03c) are supplied.

Clock signal ◇ 2b is the output of AND gate 16, return home signal?
3b is the output of the AND gate 11, and the positive signal 03c is the output of the AND gate 22 opened by the output Q2.
This is the output of These last numbers Fu2b, ◇3b,? 3c is the signal supplied to the input terminal for down counting? 1 is interrupted, the counter 19 is entered and the number of pulses is counted up. The number of pulses of these signals has the following relationship. ○3C={3600(n11)0CIt}-(〇2b+C3b) where 01t: Number of pulses of clock signal 01 generated during the timekeeping operation n: Number of pulses of the clock signal 01 generated from the carrier terminal C of the counter 19 during the timekeeping operation The number of pulses, that is, the count number of the counter 9, decreases at a rate of 1 count every second by the pulse of the signal JI from the time when the timekeeping operation state is entered, and the number corresponds to the pulse that is incremented during the timekeeping operation, By increasing the number by the sum of the number corresponding to the pulse that rapidly increased due to the return to zero, time correction information necessary when returning to clock operation is stored.

Furthermore, when the changeover switch SI is turned OFF to return to normal clock operation, the FF circuit FFI is inverted at the falling edge of the signal low 1 pulse, the logic of the output QI becomes "0", and the output QI
The logic becomes "1".

As a result, AND gates 9 and 17 are closed, and the signal ◇2
a and ◇3a are stopped, and at the same time the chronograph operation ends, the QI output of the FF circuit 1 is transferred to the FF via the differentiating circuit 8.
The time correction operation is started by setting the F circuit FF2 and inverting its output to logic "1" for Q2 and logic "0" for Q2. That is, when the AND gates 22 and 23 are opened by the output Q2 of the FF circuit FF2, the correction signal 3c causes the pulse motor PM to be fast-forwarded via the OR gate 5, and is also sent to the counter 19 via the OR gate 20 and the AND gate 21. Start counting up.

When the count number of the counter 19 reaches the set value 3600, a carrier pulse is generated at the carrier terminal C, and by resetting the FF circuits FF3 and FF2, the logic of the output Q3 of the FF circuit FF3 becomes "1". , this output Q3 opens the AND gate 4, the signal 01 is again supplied to the drive circuit 6, and the second hand starts advancing again.
Furthermore, the AND gate 18 which had been opened by the output Q3 is closed, and at this point the down-counting operation of the counter 9 is stopped, thereby completing the correction operation and returning to normal clock operation. As explained above, in this embodiment, the FF circuits FF2 and FF3 constitute a correction storage means for storing the correction state, and the clock signal 01 is generated while the correction storage means is in the operating state. is also stored in the counter 19, and is designed to return to clock operation after all time adjustments including this are completed. In addition, each FF circuit 1 to FF
4 can prevent malfunctions in the event that the signal at the time of switching is shortened by having a configuration that operates according to the falling edge of the pulse.

As explained above, according to the present invention, the difference between the displayed time and the standard time caused by the timekeeping operation is counted, and the operation of correcting the displayed time after returning to the clock operation state is automatically performed. Even for an electronic clock that generates a clock signal every second, it is possible to memorize the fact that it is being corrected, so that it can be dealt with even if a clock signal is generated during this period.

Therefore, there are advantages in that the number of operations required of the user is reduced and correction operations can be performed accurately.

[Brief explanation of the drawing]

The drawing is a block diagram showing the configuration of main parts of a fin clock according to an embodiment of the present invention. 1... Reference signal oscillator, 2... Frequency divider, 3a, 3b
, 3c... Waveform shaping circuit, 6... Drive circuit, 7, 8
... Differential circuit, 10... Zero return circuit, 12, 13...
・Differential circuit, 14...Clock circuit, 15...Differential circuit, 19...Power counter, SI, S2, S3...Switch,
PM.../Gurus Motor.

Claims (1)

[Claims] 1. Has a standard oscillator, a frequency divider, a pulse motor, and a hand-moving time display means, and performs additional function operations by also using the hand-moving time display means, and also switches between normal clock operation and additional function operation. A switching means and a clock signal storage circuit for storing a clock signal generated during the operation of the additional function are provided, and by switching the operation switching means from the additional function operation to the clock operation, the pulse motor is controlled by the information stored in the clock signal storage circuit. Accordingly, an electronic timepiece for fast forward correction is provided with a correction memory circuit which is set by the switching signal from the operation switching means and reset by the end signal of the fast forward correction operation. By configuring the clock signal that is generated while the clock signal is in the operating state to be stored in the clock signal storage circuit, normal clock operation is resumed after all the clock signals stored in the clock signal storage circuit have been corrected. An electronic clock characterized by: