JPS6139991Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an improvement of the drive circuit of a leaf-type digital watch, and particularly improves the accuracy when updating the leaves.

Leaf type digital clock is AC motor driven, DC
By rotating a drive source such as a motor drive or a DC star drive, a plurality of leaves are sequentially released from a leaf presser spring, and the time display can be updated. This leaf-type digital clock is large and can display the time in an easy-to-read manner, so it is widely used in clocks and timers. However, with leaf-type digital watches, the update operation of the time display leaf is greatly affected by the positional accuracy of the leaf and leaf-pressing spring, so it has the disadvantage that it is difficult to update the time accurately. . In other words, the leaf does not leave accurately when the time is updated, and leaves leave before or after that time.

In order to solve this problem, conventionally the leaf itself and the leaf presser spring have been molded with high precision, and the position of the leaf presser spring has been adjusted during the assembly process. But this means that the cost,
Not only has this caused serious problems regarding the work process, but it has also become difficult to accurately display the time even after position adjustment, and improvements are desired.

The present invention is an attempt to solve the conventional problems, and its purpose is to further improve the accuracy of when the leaf leaves when updating the time in a leaf-type digital watch.

In order to achieve the above objective, the present invention rotates the motor at a slower speed than usual during periods other than the update period.
By rotating the motor at a higher speed than usual near the update time, the leaf separation time is brought as close as possible to the time update time.

To this end, the present invention includes first and second counters whose sum of count times corresponds to the leaf update period, a flip-flop whose output is inverted by the output signals of the first counter and the second counter, and a flip-flop whose output is inverted according to the output signals of the first and second counters. A second counter that allows the first counter and the second counter to count alternately.
A gate circuit and an output of the flip-flop supply a low frequency pulse to the motor to rotate the motor at a low speed while the first counter is counting, and to rotate the motor at a high speed while the second counter is counting. A third gate circuit is provided to supply high-frequency pulses for this purpose.

As a result, when the time is not updated,
The display car equipped with a leaf rotates slowly, and as the update time approaches, it rotates faster, so if the configuration is such that the leaf will come off quickly,
The time between when the leaf actually leaves and when it really has to leave is short, which means the error is small. A similar effect occurs even when the leaves are slow to leave.

However, with only the above-described configuration, the actual time update time does not always occur during the period when the motor is rotating at high speed. The present invention includes an external switch, a first gate circuit that blocks the supply of pulses to the motor by turning on the external switch, and the above-mentioned a third counter that can be counted only by turning off an external switch and whose counting time is shorter than the counting time of the second counter, and the flip-flop is also inverted by the output of the third counter. The present invention is characterized in that the third gate circuit is also configured to supply high-frequency pulses to rotate the motor at high speed even while the third counter is counting. As a result, the external switch is turned on when updating the time to stop clock operation, and the switch is turned off when the displayed time and the current time match, causing the motor to rotate at high speed for the count time of the third counter. After this, the motor rotates at a low speed for the time counted by the first counter, and then rotates at high speed for the time counted by the second counter. The sum of the count times of the first and second counters exactly matches the time update cycle, that is, the leaf departure cycle, so the motor always rotates at high speed before and after the true time when the leaf should leave. It turns out.

Hereinafter, the present invention will be explained in detail based on preferred embodiments.

FIG. 1 shows an external view of the main parts of the leaf type digital clock according to the present invention, and the clock receiving plate 10 has a
Minute indicator 12, 10 minute indicator 14 and hour indicator 1
6 is rotatably supported. Each display car 12,
14 and 16 each have a plurality of one-minute leaves 18, ten-minute leaves 20, and hour leaves 22 on their peripheries. Although not shown in detail, as is well known, each display wheel 12, 14, and 16 is driven by a drive source such as a motor, and is configured to display a predetermined time. Generally, when a DC-driven synchronous motor is used as a drive source, the motor is configured to be driven at 64 Hz. Further, when a step motor is used as a drive source, it is configured to be driven at 1 Hz.
Suitable for the receiving plate 10 are a 1-minute leaf presser spring 30 for positioning and holding the 1-minute leaf 18, a 10-minute leaf presser spring 32 for positioning and holding the 10-minute leaf 20, and a leaf presser spring 34 for positioning and holding the hour leaf 22. Fixed in position. Each leaf presser spring 30, 32 and 34 has its elastic tongue 30
a, 32a and 34a connect the tips of each leaf 18, 20 and 22 to each leaf 18, 20 and 22.
The leaves 18, 20, and 22 are held in a substantially vertical position, and each leaf 18, 20, and 22 is released and updated at a predetermined time by rotation of each display wheel 12, 14, and 16. On the other hand, the second display wheel 40 has a second display scale attached to its circumferential surface, and is rotated by a driving source to display the second time by rotating once per minute.

Figure 2 shows the first embodiment of the present invention in which a synchronous motor is used as the drive motor, and Figure 3 shows the second embodiment of the invention.
This is a time chart in the figure.

FIG. 2 shows a drive circuit when a synchronous motor is used as the drive motor, and it includes an oscillator 100, a frequency divider 102, flip-flops 104, 106,
108...136, 138, and gate 140,
142, 144...160, 162, 190, OR gates 164, 166, an inverter 168, a reset switch 170, and an amplifier circuit 172. The oscillator 100 generates a time reference signal, and the frequency divider 102
This is a circuit that frequency-divides the signal from 1Hz to 1Hz. Further, a 128 Hz signal 101 used as a high frequency pulse and a 32 Hz signal 103 as a low frequency pulse are output from the middle of the frequency division stage of this frequency divider 102. On the other hand, the 1 Hz signal frequency-divided by frequency divider 102 is input as a clock signal to flip-flops 104, 106, and 108. These flip-flops 104, 106, 108 and the AND gate 140,
142 constitutes an octal counter 109. The output signal of the output _Q1 of the flip-flop 108, which is the 109 output of this octal counter, is inputted as a clock signal to the flip-flops 110, 112, and 114. This flip-flop 110, 11
2,114 and an AND gate 144 constitute a quinary counter. Therefore, this octal counter 1
09 and the quinary counter 115 constitute a 40-decimal counter 117 as a first counter. The output Q ₂ of the flip-flop 114, which is the output of the 40-decimal counter 117, is input to one of the input terminals of the OR gate 164. The 1 Hz signal is also input as a clock signal to flip-flops 116 and 118. This flip-flop 11
6,118 constitute a quaternary counter 119. The output _Q3 of flip-flop 118, which is the output of quaternary counter 119, is output from flip-flop 1.
It is input as clock signals of 20, 122, and 124. This flip-flop 120, 12
2,124 and an AND gate 146 constitute a quinary counter 125. Therefore, by this quinary counter 125 and quaternary counter 119, the second
A 20-decimal counter 127 is configured as a counter. The output _Q4 of the flip-flop 124, which is the output of the 2decimal counter 127, is the OR gate 1.
64 input terminals. Also, the 1Hz output signal is output from flip-flops 126, 128, 1
It is also input as a clock signal of 30 and 132. This flip-flop 126, 128, 13
0,132 and AND gate 148,150,15
2,154 constitutes a hexadecimal counter 133. The output _Q5 of flip-flop 132, which is the output of this hexadecimal counter, is output from flip-flop 134.
input as the clock signal. The output Q ₆ of this flip-flop 134 is connected to the input J ₆ and the input K ₆ is grounded. Also, the output _Q6 of the flip-flop 134 is the output of the flip-flop 134.
It is input to the reset terminal of 8. A reset switch 170 is connected to the clock input of flip-flop 138. This hex counter 13
3 and flip-flops 134 and 138
A counter 139 is configured. The output signal from reset switch 170 is input to the reset terminal of flip-flop 136 via inverter 168. On the other hand, the output of flip-flop 138
Q ₇ includes flip-flops 126, 128, 130, 132 that constitute a hexadecimal counter 133;
It is input to the reset terminal of flip-flop 134. Also, the output Q ₇ of flip-flop 138
is input to one of the input terminals of AND gates 156 and 158 constituting the second gate circuit 155. The output Q ₈ of the flip-flop 136 is input to the other input terminal of the AND gate 156, and the output Q ₈ of the flip-flop 136 is input to the other input terminal of the AND gate 158. And the output signal of AND gate 156 is 20
The output of the AND gate 158 is input to the reset terminals of the flip-flops 116, 118, 120, 122, and 124 that make up the 40-decimal counter 117.
It is input to the reset terminal of 2,114.

On the other hand, the output Q ₅ of the flip-flop 132 is also input to one of the input terminals of the OR gate 164.
The output signal of the OR gate 164 is input as a clock signal to the flip-flop 136.
The output _Q8 of the flip-flop 136 is input to one input terminal of an AND gate 160, and the other input terminal of the AND gate 160 is connected to a frequency divider 1.
A 32Hz signal 103 from the middle of the frequency dividing stage of 02 is input. Also, the output of flip-flop 136
Q ₈ is input to one input terminal of the AND gate 162, and the 128 Hz signal 101 from the middle of the frequency division stage of the frequency divider 102 is input to the other input terminal of the AND gate 162. This flip-flop 136 and OR gate 164 constitute a flip-flop circuit 165. And gate 1
The output 161 of the AND gate 160 is directly input to the OR gate 166, and the output 163 of the AND gate 162 is input to the OR gate 166 via the AND gate 190. The output signal of the inverter 168 is input to the other input terminal of the AND gate 190.
The AND gates 160, 162 and the OR gate 166 constitute a third gate circuit 167, and the AND gate 190 and the inverter 168 constitute a first gate circuit 191.

Next, the operation of this circuit will be explained. In this circuit, when nothing is connected to the J and K inputs of the flip-flop, an H-level signal is input, and the flip-flop operates when the signal input to the clock input falls from the H level to the L level. shall be taken as a thing.

First, when the reset switch 170 is closed during the minute update, the output of the synchronous motor 174 is stopped, and the third
An H level signal 169 as shown in the figure is output,
The signal is inverted by the inverter 168 to become L level, and is input to the reset terminal of the flip-flop 136, thereby resetting the flip-flop 136. As a result, as shown in FIG. 3, the output _Q8 of the flip-flop 136 becomes H level, and the output _Q8 becomes L level, so that
0 is closed and AND gate 162 is open. Therefore, a 128Hz signal is generated at the output 163 of the AND gate 162, but since the other input of the AND gate 190 is at L level, no 128Hz signal is input to the synchronous motor 174, so the rotation stops. It remains as it is.

Then, when the current time matches the time displayed on the clock, when the reset switch 170 is opened, the output 169 falls from the H level to the L level as shown in FIG. 3, the output _Q7 of the flip-flop 138 goes to the H level, and the output QQ ₇ is inverted to L level. As a result, an L level signal is input to one of the input terminals of AND gates 156 and 158, and since the output becomes L level, the 20-decimal counter 127 and the 40-decimal counter 117 are reset. Also flipflop 1
The output _Q7 of 38 releases hex counter 133 and flip-flop 134 from reset. 16 to this
The advance counter 133 starts counting.

On the other hand, since the output 169 of the reset switch 170 changes from the L level to the H level signal via the inverter 168, the reset of the flip-flop 136 is released, the AND gate 190 is opened, and the synchronous motor 174 starts driving. In this state, the output of flip-flop 136 is
Since Q ₈ and Q ₈ are the same as when the reset switch 170 is closed, the amplifier circuit 1 of the synchronous motor 174
A 128 Hz signal as shown in FIG. 3 is input to the synchronous motor 174 through the OR gate 166.
rotate faster. After 16 seconds, the output _Q5 of the flip-flop 132, which is the output of the hexadecimal counter, falls from the H level to the L level, so the output _Q6 of the flip-flop 134 is inverted from the H level to the L level. This causes flip-flop 13
8 is reset, and its output _Q7 goes to L level and outputs hexadecimal counter 133 and flip-flop 13.
Reset 4.

On the other hand, the falling signal from the output _Q5 of flip-flop 132 is input to the clock input of flip-flop 136 through OR gate 164.
As a result, as shown in FIG. 3, the output _Q8 of the flip-flop 136 is inverted to H level, and _Q8 is inverted to L level. Therefore, AND gate 162 is closed, AND gate 160 is opened, and OR gate 16 is closed.
At the output 167 of 6, a 32Hz signal is generated instead of the 128Hz signal. Therefore, the rotation of the synchronous motor 174 becomes slow. At the same time, the output signal of the AND gate 158 becomes H level due to the H level output signal of the output _Q8 of the flip-flop 136, thereby canceling the reset of the 40-decimal counter 117 and starting counting. When 40 seconds have elapsed, a falling signal from the output _Q2 of flip-flop 114, which is the output of 40-decimal counter 117, is input to the clock input of flip-flop 136 through OR gate 164. As a result, the output of flip-flop 136 as shown in FIG.
_Q8 is inverted to L level and _Q8 is inverted to H level. When that happens, the AND gate 160 closes,
AND gate 162 opens. Therefore, the output 163 of the AND gate 162 is as shown in FIG.
A 128Hz signal is generated, and the output 161 of the AND gate 160 becomes L level. Therefore, a 128Hz signal is generated at the output 167 of the OR gate 166,
The synchronous motor 174 rotates quickly again. At the same time, the outputs Q ₈ and Q ₈ of the flip-flop 136
As a result, AND gate 158 outputs an L level signal, and AND gate 156 outputs an H level signal. Therefore, the 40-decimal counter 117 is reset, and the 20-decimal counter 127 is released from the reset and starts counting. When four seconds have passed in this state, one minute has passed since the reset switch 170 was opened, so the leaf is updated. In this case, since the synchronous motor 174 rotates at high speed in response to the 128 Hz signal, the time when the minutes are updated and the time when the leaves are updated match with higher accuracy.

When 20 seconds have elapsed since the 20-decimal counter 127 started counting, the falling signal from the output _Q4 of the flip-flop 124, which is the output of the 20-decimal counter 127, is input to the flip-flop 136 through the OR gate 164, and as shown in FIG. Its output as shown
AND gate 160 opens and AND gate 162 closes to invert Q ₈ and Q ₈ . Therefore, the output 161 of the AND gate 160 outputs a 32 Hz signal as shown in FIG. 3, and the output of the AND gate 162 becomes L level. Therefore, or gate 1
The output 167 of 66 generates a 32Hz signal. This causes the synchronous motor 174 to rotate slowly again. On the other hand, at the same time, AND gates 156 and 158 are inverted due to the inversion of the outputs Q ₈ and Q ₈ of flip-flop 136.
outputs an H level signal, and the AND gate 156
The output becomes L level. Therefore, the reset of the 40-decimal counter 117 is canceled and the above-described operation is repeated. To repeat this operation, the output 163 of the AND gate 162 maintains the L level signal for 40 seconds as shown in FIG.
Outputs a Hz signal for 20 seconds. Also and gate 1
As shown in FIG. 3, the output 161 of 60 outputs a 32 Hz signal for 40 seconds after that, maintains the L level signal for 20 seconds, and then outputs a 32 Hz signal again for 40 seconds. Therefore, the output 167 of the OR gate 166
will output a 32Hz signal for 40 seconds and a 128Hz signal for 20 seconds.
Repeat output for seconds. In the first embodiment of the present invention, the setting is such that every time a 128 Hz signal is output for 20 seconds, it is time to update the minute 4 seconds after the 128 Hz signal begins to be output, and the leaf is updated.

Generally, a synchronous motor rotates at a constant rate using a 64Hz signal. In this invention, there are two types (128Hz, 32Hz).
Hz) signal, but the number of rotations per minute is the same as when rotating with a 64Hz signal.

On the other hand, the display wheel 40 shown in FIG. 1 needs to be rotated once per minute at a constant rotation rate. It is necessary to set the gear pitch of the display wheel drive wheel train to correspond to the drive signal. Alternatively, a configuration may be implemented in which a drive motor for rotating only the second indicator wheel 40 is attached and the motor is set to rotate at a constant speed.

FIG. 4 is a time chart when a step motor is used as the drive motor as a second embodiment of the present invention. The 2 Hz step pulse and the 1 Hz step pulse shown in the time chart of Fig. 4 are respectively generated by the frequency divider 1 shown in Fig. 2.
It is constructed by taking several outputs from the frequency dividing stage of 02. The drive output of the step motor as shown in FIG. 4 is input to the step motor. In the second embodiment of the present invention, instead of the hexadecimal counter, 40-decimal counter, and 20-decimal counter of the first embodiment, a binary counter, a 52-decimal counter, and a 20-decimal counter are used.
This uses four four-digit counters. To explain the above drive output in detail, first, when the reset switch changes from the closed state to the open state, a binary counter outputs a 2Hz pulse to the step motor for 2 seconds (drive output interval a), and then a quaternary counter outputs a 2Hz pulse to the step motor for 2 seconds (drive output interval a). The counter stops the pulse for 4 seconds (drive output interval b). After that, the 52-decimal counter is set to 1 for 52 seconds.
Output Hz pulses to the step motor (drive output interval c). After that, another 4-ary counter outputs a 2 Hz pulse for 4 seconds (drive output interval d). The leaf will be updated two seconds after this 2Hz pulse is input to the step motor, or one minute after the reset switch is opened.

Thereafter, the drive output repeats the drive output intervals b, c, and d. As another example, it is also possible to send only 2 Hz pulses to the step motor for 30 seconds including the leaf update time, and stop the step motor without sending any pulses for the remaining 30 seconds.

As described above, according to the present invention, the accuracy during leaf updating can be further improved by rotating the motor at high speed around the time of leaf updating and rotating at low speed during other periods.

[Brief explanation of the drawing]

FIG. 1 is an external view of the main parts of the leaf-type digital watch according to the present invention. FIG. 2 is a circuit diagram showing a first embodiment of the present invention in which a synchronous motor is used as the drive motor. Figure 3 is a time chart in Figure 2.
FIG. 4 is a time chart showing a second embodiment of the present invention in which a step motor is used as the drive motor. 18, 20, 22...display leaf, 30, 3
2, 34...Leaf presser spring, 117...40-decimal counter, 127...20-decimal counter, 133...16
Advance counter, 136...Flip-flop, 16
0,162...AND gate, 166...OR gate, 174...Synchronous motor.

Claims (1)

[Scope of utility model registration request] an oscillator that generates a reference signal; a frequency dividing circuit that divides the frequency of the reference signal from the oscillator; a motor that is rotationally driven by the output signal from the frequency dividing circuit; In a leaf type digital clock having a display wheel having a plurality of leaves, and a leaf holding spring for positioning and holding the leaf and updating the leaf at a constant cycle, each output signal of the frequency dividing circuit is counted. a first counter and a second counter whose total time corresponds to a leaf update period; an external switch; a first gate circuit that blocks pulse supply to the motor by turning on the external switch; and a first gate circuit that turns off the external switch. a third counter that can count the output signal of the frequency dividing circuit only by operation and whose count time is shorter than the count time of the second counter; and output signals of the first, second, and third counters. A flip-flop whose output is inverted by
a second gate circuit that enables the first counter and the second counter to count alternately by the output of the flip-flop; supplying output pulses to the motor;
A drive circuit for a leaf-type digital timepiece, comprising: a third gate circuit that supplies an output pulse of a higher frequency than usual from the frequency dividing circuit to the motor while the counter is counting.