JPS6322276B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a computer timepiece having a time correction function, which detects errors inherent in the timepiece including original oscillation from the difference between a reference time signal and the internal time of the timepiece.
The purpose is to output accurate time by correcting the time based on the error.

Conventional computer clocks of this type correct the time to the reference time the instant they receive the reference time signal. However, errors in the primary oscillation occur due to changes in the environment or changes in parts over time, and not only does the time before the correction lack accuracy, but the increase in correction values can cause problems such as times disappearing or overlapping.

This type of clock is used, for example, in a train car guidance system, and when a predetermined time has arrived, it outputs the time in a voice. In this automatic departure guidance system, for example, suppose that a clock that adjusts the time with 12:00:00 as the reference time is 5 seconds ahead. If this clock is used to provide car guidance for a train departing at 12:00:00, the time will return to 12:00:0 after 5 seconds, so the same guidance will be given again. On the other hand, if the train is late, the time will be skipped by the amount of time the train is late, and the train will not be able to provide guidance for the departing train during that time.

As described above, there are problems with conventional time adjustment especially when performing real-time processing as a clock for a computer system.

The present invention eliminates these drawbacks, and one embodiment of the present invention will be described below with reference to the drawings. Figure 1 is this block diagram, where 1 is the oscillation part,
2 is a correction circuit, 3 is a correction control section, 4 is a storage section, 5
6 is a calculation unit, 6 is a reference time setter, 7 is a time counter for determining clock time, and 8 is a reference time reception signal obtained by a receiving circuit or the like.

Figure 2 is a reference diagram for explaining this operation.
8-0, 8-1, 8-2, and 8-3 are reference times, and their period is T. T _A , T _B , and T _C are the cycles specific to the clock of the present invention, A, B, and C are the points at which the internal time of the clock of the present invention becomes the reference time, a, b, and c are the errors at that time, A, B, C is a period during which time correction is performed by the timepiece of the present invention, and V _A , V _B , and V _C are correction values at that time.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

First, assume that the main clock is delayed and receives the reference time signal in Figure 2 (b). At this time, the arithmetic unit 5 calculates the difference b between the value b of the time counter 7 and the value 8-1 of the reference time setter 6. Next, the current correction value V _B is calculated from the correction value V _A performed in the previous figure A stored in the storage unit 4, the error determined at the previous time A, and the error b just obtained.
seek.

Here, from Fig. 2, the error inherent to this watch during period A is T _A = T- (V _A + b - a), so V _A + b -
It turns out that it is a. Also, since the error b has already occurred at the time of b, in the end, this time V _B = (V _A + b -
It is sufficient to correct it by setting a)+b...1. This calculation is executed in the calculation unit 5, and the current error b
and the correction value V _B are updated to the previous a and V _A and stored in the storage unit 4.
is stored in The correction control unit 3 divides the reference time signal period T by the value of V _B in the storage unit 4 and obtains the quotient (denoted as t). Then, a correction command is issued to the correction circuit 2 every time the time t elapses. The correction circuit 2 corrects the time by adding (+1) or (-1) the value of the time count that counts the number of oscillations at the timing when the command is received. As a result, the time is gradually corrected at equal intervals.

This will be explained using a numerical example. If the standard time setter is set to receive the standard time signal at 7:00:00 every day, 8-0 to 8-3 are the correct 7:00:0, and A, B, and C are the clock's internal times. The time is 7:00:00. where a = 1 second, T _A = 23 hours
If it is 59 minutes and 57 seconds and the correction value V _A for period A is +2 seconds (+ means advance), then B, which the clock judged to be 7:00:00, would actually be 6:59.
It is 58 seconds. Therefore, if the reference time signal of 8-1 is received at the internal time of 7:00:2, the error b =
It will be 2 seconds. At this time, the value of the next correction value V _B will be +5 seconds according to equation 1. The purpose of the present invention is to distribute error correction as evenly as possible, and in this embodiment, correction is performed in units of 1 millisecond. In this case, the correction period is [86400000 milliseconds (1 day) ÷ (5000 +
1)] = 17276 milliseconds, a correction will be performed to advance the time by 1 millisecond every 17276 milliseconds. Here, [ ] is the decimal part of the division. Normally, if V _B is corrected during period B, the error C at time C will disappear, but if the error inherent to the clock changes during this period, an error (T _A < T _B ) and an error (C > 0) will occur. Suppose that

At this time, as before, V _C = (V _B - c - b) - c
The error can be eliminated by correcting.

As is clear from the above embodiments, the present invention compares the signal of the time counter and the reference time reception signal at a desired time every day, calculates the current correction value together with the previous correction value, and In order to correct the correction, we output a correction control signal at equal intervals of approximately 1 millisecond each time, and corrected the number of output pulses of the oscillator. This has the effect that even if an error occurs in the original oscillation, there will be no disappearance or overlap of time due to an increase in the correction value, and no disappearance or overlap of automatic departure guidance etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a computer timepiece according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of the same timepiece. DESCRIPTION OF SYMBOLS 1... Oscillation part, 2... Correction circuit, 3... Correction control part, 4... Storage part, 5... Arithmetic part, 6... Reference time setter, 7... Time counter, 8... Reference time received signal.

Claims (1)

[Claims] 1. An oscillator that oscillates the clock internal time signal, a reference time setter that can be set to receive the reference time reception signal at a desired time every day, and a reference time setter that oscillates the clock internal time signal each time a control signal is input. a correction circuit that increases or decreases the number of pulses; a time counter that counts the output signal of this correction circuit and outputs a time signal;
This time signal is compared with the reference time reception signal, and the current correction value is calculated along with the previous correction value, and the correction is completed approximately once per day.
a calculation unit that gradually performs correction at equal intervals of milliseconds; a storage unit that stores the correction interval of the calculation unit; and a correction control that outputs the control signal to the correction circuit at each correction interval of the storage unit. A computer clock with a