JPS5850031A - Time correcting system for computer - Google Patents

Time correcting system for computer

Info

Publication number
JPS5850031A
JPS5850031A JP56147812A JP14781281A JPS5850031A JP S5850031 A JPS5850031 A JP S5850031A JP 56147812 A JP56147812 A JP 56147812A JP 14781281 A JP14781281 A JP 14781281A JP S5850031 A JPS5850031 A JP S5850031A
Authority
JP
Japan
Prior art keywords
time
computer
correction
timer
correction quantity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56147812A
Other languages
Japanese (ja)
Inventor
Fumiaki Miyamoto
宮本 文明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Information and Control Systems Inc
Original Assignee
Hitachi Ltd
Hitachi Control Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Control Systems Inc filed Critical Hitachi Ltd
Priority to JP56147812A priority Critical patent/JPS5850031A/en
Publication of JPS5850031A publication Critical patent/JPS5850031A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Control By Computers (AREA)

Abstract

PURPOSE:To secure the uniformity and the precision of a processing, by executing the correction plural times for an overall correction quantity and correcting a unit correction quantity every one step of the correction. CONSTITUTION:In the conventional device, a timer correcting part 6 is connected to a timer processing mechanism 4. In case that the time in a computer which is slow is set forward, a unit correction quantity is subtracted from the preset value of a timer processing mechanism 3 to generate a driving signal 13 for the elapse of T-(the unit correction quantity) to the required time T of time counting, and thus, the current time in the computer is set forward by the unit correction quantity. In case that the time in the computer which is fast is set backward, the preset value is added to the unit correction quantity to generate the driving signal 13 for the elapse of T+(the unit correction quantity) to said required time T, and thus, the current time in the computer is set backward by the unit correction quantity.

Description

【発明の詳細な説明】 本発明は計算機の時刻補正方式に係シ、特にプロセスの
計測制御を行なう計算機に好適な計算機の時刻補正方式
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time correction method for a computer, and more particularly to a time correction method for a computer suitable for a computer that performs measurement control of a process.

第1図は電子計算機に用いられた従来のタイマー処理装
置のブロック図である。
FIG. 1 is a block diagram of a conventional timer processing device used in an electronic computer.

水晶発振器1にて発生した数10MH2の発振器出力パ
ルス11は、周波数低減装置2にて、100 MHz 
 〜I MHzのタイマーベース出力12に低減され、
タイマー処理機構[F]3に駆動する。このタイマー処
理慎構3は、プリセットされていたタイマーカウンタ5
をカウントダウンし、カウント完了時にタイマー処理機
構(S)4に駆動信号13を出力する。この処理を示し
たのが第2図のフローチャートである。駆動信号13を
入力信号とするタイマー処理機構(S)4は、13にて
駆動され、前回プリセットした値Nと、タイマーベース
時間t(タイマーベース周波数の逆数)によりT=NX
 t と の時間経過像認識し、計時(現在時刻の実新)を行なう
。この処理を示したのが第3図のフローチャートである
。この更新処理は、例えばt = l m秒、N=10
00とした場合には、T=1秒の経過を認識し、計算機
内の時刻を1秒歩進する。
The oscillator output pulse 11 of several tens of MHz generated by the crystal oscillator 1 is reduced to 100 MHz by the frequency reduction device 2.
~I MHz timer base output reduced to 12,
The timer processing mechanism [F]3 is driven. This timer processing system 3 is a preset timer counter 5.
is counted down, and when the count is completed, a drive signal 13 is output to the timer processing mechanism (S) 4. The flowchart in FIG. 2 shows this process. The timer processing mechanism (S) 4 which receives the drive signal 13 as an input signal is driven by the drive signal 13, and T=NX based on the previously preset value N and the timer base time t (reciprocal of the timer base frequency).
It recognizes the time lapse image with respect to t and performs time measurement (actual update of the current time). The flowchart in FIG. 3 shows this process. This update process takes, for example, t = l m seconds, N = 10
If it is set to 00, it is recognized that T=1 second has passed, and the time in the computer is incremented by 1 second.

かかる従来の計時機構においては、10”’〜10−4
程度の水晶発振器の誤差により、計時誤差は、1ケ月に
数秒〜数分になり、定期的に時刻の補正を要す、補正は
、1日〜10数日毎に行なうのが一般的である。
In such conventional timekeeping mechanisms, 10"' to 10-4
Due to the error of the crystal oscillator, the time measurement error is several seconds to several minutes per month, and the time must be corrected periodically.The correction is generally performed every 1 to 10-odd days.

ところで、かかる従来の補正処理に際しては2つの欠点
がある。即ち、その第1は、時刻を戻した場合の同一時
刻帯における2重通過もしくは、時刻を進めた場合の空
白時刻帯の出現であり、そ9第2は、時刻より求めた時
間帯(例えば、5分間、1時間)に対応するプロセス計
測情報のデータの劣化である0例えば、時刻を1分間進
めた時間帯の時間積算値は、22%程度の誤差が生じる
However, such conventional correction processing has two drawbacks. That is, the first is the occurrence of double passage in the same time zone when the time is set back, or the appearance of a blank time zone when the time is advanced. , 5 minutes, and 1 hour).For example, the time integrated value for a time period in which the time is advanced by 1 minute has an error of about 22%.

本発明の目的は、処理の均一性と精度の確保に必要な時
刻補正を行うことのできる計算機の時刻補正方式を提供
するにある。
An object of the present invention is to provide a time correction method for a computer that can perform time correction necessary to ensure uniformity and accuracy of processing.

本発明は、従来の時刻補正の欠点が数日間に及ぶ長時間
の誤差の累積を補正要求時において一度に補正すること
に起因することに着目し、全補正量を単位補正量と補正
回数に変換し、単位補正量と単位補正量分の補正実行時
間隔をシステム上許容される組合せで選択することによ
り補正を行うようにしたものである。
The present invention focuses on the fact that the drawback of conventional time correction is that the accumulation of long-term errors over several days is corrected at once when a correction is requested, and converts the total correction amount into a unit correction amount and the number of corrections. The correction is performed by selecting a combination of the unit correction amount and the correction execution time interval for the unit correction amount in a system-permissible combination.

第4図は本発明の実施例を示すブロック図である。第5
図は第4図の実施例の処理フローチャートである。第4
図においては第1図に示した部材と同一部材であるもの
には同一符号を用いている。
FIG. 4 is a block diagram showing an embodiment of the present invention. Fifth
The figure is a processing flowchart of the embodiment of FIG. 4. Fourth
In the figures, the same reference numerals are used for the same members as those shown in FIG.

また、本実施例においては、補正実行間隔を計時間隔と
同一にした場合を扱っている。本実施例は第4図よシ明
らかな如くタイマー補正部6をタイマー処理機構4に接
続したものであり、該タイマー補正部6は補正要求判定
、単位補正量および補正回数の決定を行う機能を有し、
これに基づいてタイマー処理機構4が更新処理を行うも
のである。
Furthermore, this embodiment deals with a case where the correction execution interval is made the same as the time measurement interval. In this embodiment, as is clear from FIG. 4, a timer correction section 6 is connected to the timer processing mechanism 4, and the timer correction section 6 has the functions of determining a correction request, a unit correction amount, and the number of corrections. have,
Based on this, the timer processing mechanism 4 performs update processing.

他の構成ならびに機能については第1図の構成と同一で
あるので説明を省略する。
The other configurations and functions are the same as those shown in FIG. 1, so their explanations will be omitted.

計算機内時刻が遅れていて「進める」場合は、タイマー
処理機構3のプリセット値を単位補正量分域することに
より、計時所要間隔Tに対し、(T一単位補正量)、の
経過で、駆動信号13が発生し、計算慎内の現在時刻を
単位補正量分だけ進めることが出来る。
If the internal time in the computer is delayed and you want to advance it, by dividing the preset value of the timer processing mechanism 3 into the unit correction amount, the drive will be started at the elapsed time of (T - unit correction amount) for the required time interval T. A signal 13 is generated, and the current time in the calculation table can be advanced by the unit correction amount.

また、計算機内時刻が進んでいて「鴻らせる」場合はプ
リセット値を単位補正量分加えておくことにより、計時
所要間隔Tに対し、(T千単位補正量)の経過で、駆動
信号13が発生し、計算機内現在時刻を単位補正量分遅
らせることが出来る。
In addition, if the internal time in the computer is advanced and becomes "cloudy", by adding the preset value by the unit correction amount, the drive signal 13 occurs, and the current time in the computer can be delayed by the unit correction amount.

本実施例によれば、時刻の2重通過、空白時間帯が生じ
ないとともに、データの誤差の最大時、(巣位補正量/
補正実行間隔)に改善される。
According to this embodiment, double passage of time and blank time periods do not occur, and when the data error is maximum, (focal position correction amount /
correction execution interval).

第6図は本発明の他の実施例を示すブロック図であり、
第7図は第6図の実施例の処理フローチャートである。
FIG. 6 is a block diagram showing another embodiment of the present invention,
FIG. 7 is a processing flowchart of the embodiment of FIG.

本実施例においても第1図に示したと同一部材であるも
のには同一符号を用いている。本実施例は、補正実行間
隔を計時間隔より大きくする場合を対象としている。本
実施例は第4図の実施例にタイマー補正機構71&:付
加したものであり−1該タイマー補正機構7はタイマー
補正部6の出力およびタイマー処理機構4より補正実行
間隔の経過において出力される補正処理駆動信号15に
基づいて駆動される。タイマー補正機構7のプリセット
はタイマー処理機構4によって行われ、タイマー処理機
構3によりカウントダウンされる、カウンタ5の内容を
単位補正量だけ加減することにより、次に出力される駆
動信号13を進ませ、または遅らせることができる。
In this embodiment as well, the same reference numerals are used for the same members as shown in FIG. This embodiment is intended for a case where the correction execution interval is made larger than the time measurement interval. This embodiment has a timer correction mechanism 71&: added to the embodiment shown in FIG. It is driven based on the correction processing drive signal 15. The presetting of the timer correction mechanism 7 is performed by the timer processing mechanism 4, and the content of the counter 5, which is counted down by the timer processing mechanism 3, is adjusted by a unit correction amount to advance the drive signal 13 to be output next. or can be delayed.

本実施例は第4図の実施例による効果に加え、データの
誤差の最大を任意に設定できる効果を有している。
In addition to the effects of the embodiment shown in FIG. 4, this embodiment has the advantage that the maximum data error can be set arbitrarily.

以上詳述したように本発明の実施例によれば、従来時刻
補正時に発生していた同一時刻の2重通過もしくは空白
時間帯の発生を防止でき、また、補正によるデータの劣
化すなわち誤差の増加を少なくすることができる。具体
的に一例をあげれば、単位補正量を1m秒、補正実行間
隔を1秒、全補正量を1分とした場合、誤差の最大は、
0.1%であり、従来方式での1時間値の誤差1.7%
、15分位の誤差6.7%、5分値の誤差20%であっ
たのを大巾に改善できる。
As described in detail above, according to the embodiments of the present invention, it is possible to prevent double passage of the same time or the occurrence of a blank time period, which conventionally occurred during time correction, and also to prevent data deterioration due to correction, i.e., an increase in errors. can be reduced. To give a specific example, if the unit correction amount is 1 ms, the correction execution interval is 1 second, and the total correction amount is 1 minute, the maximum error is:
0.1%, and the error in the 1-hour value using the conventional method is 1.7%.
, the error in the 15th decimal point was 6.7%, and the error in the 5th minute value was 20%, but this can be greatly improved.

以上より明らかな如く本発明によれば、計測制御に必要
な処理の均一性と精度を確保することができる。
As is clear from the above, according to the present invention, it is possible to ensure the uniformity and accuracy of processing necessary for measurement control.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のタイマー処理装置のブロック図、第2図
は第1図の装置のタイマー処理機構3の処理フローチャ
ート、第3図は第1図の装置のタイマー処理機構4の処
理フローチャート、第4図は本発明の実施例を示すブロ
ック図、第5図は第4図の実施例の処理フローチャート
、第6図は本発明の他の実施例を示すブロック図、第7
図は第6図の実施例の処理フローチャートである。 1・・・水晶発振器、2・・・周波数低減装置、3・・
・タイマー処理機構、4・・・タイマー処理機構、5・
・・タイマーカウンタ、6・・・タイマー補正部、7・
・・タイマ篇5図
1 is a block diagram of a conventional timer processing device, FIG. 2 is a processing flowchart of the timer processing mechanism 3 of the device shown in FIG. 1, and FIG. 3 is a processing flowchart of the timer processing mechanism 4 of the device shown in FIG. 4 is a block diagram showing an embodiment of the present invention, FIG. 5 is a processing flowchart of the embodiment of FIG. 4, FIG. 6 is a block diagram showing another embodiment of the present invention, and FIG.
The figure is a processing flowchart of the embodiment of FIG. 1... Crystal oscillator, 2... Frequency reduction device, 3...
・Timer processing mechanism, 4... Timer processing mechanism, 5.
...Timer counter, 6...Timer correction section, 7.
・・Timer version 5 diagram

Claims (1)

【特許請求の範囲】[Claims] 1、発振器の出力パルスを原情報として計時を行なう計
算機の、発振器出力精度に起因する計時誤差を、他情報
にて補正する計算機の時刻補正方式において、全補正量
を複数の補正実行回数に分けると共に、そのlステップ
補正ごとに前記補正量のうちの単位補正量だけを補正す
ることを特徴とする計算機の時刻補正方式。
1. In the time correction method of a computer that uses other information to correct the time measurement error caused by the accuracy of the oscillator output of a computer that measures time using the oscillator output pulse as the original information, the total amount of correction is divided into multiple correction execution times. and a time correction method for a computer, characterized in that only a unit correction amount of the correction amount is corrected for each l-step correction.
JP56147812A 1981-09-21 1981-09-21 Time correcting system for computer Pending JPS5850031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56147812A JPS5850031A (en) 1981-09-21 1981-09-21 Time correcting system for computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56147812A JPS5850031A (en) 1981-09-21 1981-09-21 Time correcting system for computer

Publications (1)

Publication Number Publication Date
JPS5850031A true JPS5850031A (en) 1983-03-24

Family

ID=15438768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56147812A Pending JPS5850031A (en) 1981-09-21 1981-09-21 Time correcting system for computer

Country Status (1)

Country Link
JP (1) JPS5850031A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154540U (en) * 1986-03-25 1987-10-01
JPH08328691A (en) * 1995-05-29 1996-12-13 Mitsubishi Electric Corp Time synchronization device in remote supervisory controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154540U (en) * 1986-03-25 1987-10-01
JPH08328691A (en) * 1995-05-29 1996-12-13 Mitsubishi Electric Corp Time synchronization device in remote supervisory controller

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