JPH06174865A - Control clock device - Google Patents

Abstract

PURPOSE:To automatically adjust gain or loss due to errors in an oscillator. CONSTITUTION:A period of seconds for correcting error is set by an error- correcting second setting means 5 to adjust gain or loss due to errors in an oscillator built into a timer 1. At a predetermined time an error-correcting count variation means 6 issues a command to vary the number of seconds in one minute to a counting means 2. According to the command from the error-correcting count variation means 6, the counting means 2 counts the period of seconds for correcting an error of sixty seconds in place of counting a period of sixty seconds at the predetermined time, thereby automatically correcting the gain or loss of the seconds for correcting error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timepiece device for control used for time control of various control devices which control using a computer.

[0002]

2. Description of the Related Art Most of recent control devices such as electric water heaters use computers for control. The computer has a built-in timer that outputs a clock signal based on a pulse signal from a vibrator, and conventionally, a timer device for control that uses this timer to know the time for control is configured.

[0003]

However, the oscillator (crystal oscillator, etc.) always has a precision error, and the precision error causes a delay or advance in time. The conventional control timepiece has a function of periodically correcting this delay or advance to adjust the time, but it is not possible to fundamentally adjust the delay or advance based on the accuracy error of the oscillator. It was

SUMMARY OF THE INVENTION An object of the present invention is to provide a control timepiece device in which the delay or advance amount based on the error of the vibrator can be adjusted in units of seconds so that the time adjustment cycle can be extended as long as possible. .

[0005]

According to the invention of claim 1, a timer incorporated in a computer is used, and the display of the minute is advanced by 1 minute every 60 seconds counted by the output of the timer. For the control timepiece device, the error adjustment second setting means for setting the error adjustment seconds and 60 seconds ± 60 seconds ± the error adjustment seconds instead of counting 60 seconds at a predetermined time, display one minute. And an error adjusting means for advancing by an amount.

The predetermined time may be an appropriate time of the day, or may be an appropriate time of some days for a timer having a calendar function.

Since the clock signal output from the timer is created with reference to the pulse signal from the oscillator, when the clock signal is output at a cycle of 1 second, the error adjustment seconds are in units of 1 second. When the clock signal is output in a cycle shorter than 1 second, the error adjustment second can be set to a unit of 1 second or less.

[0008]

[Function] Delay or advance due to the error of the oscillator is 1 per day
If it is seconds, the display may be automatically delayed or advanced by 1 second every day. In the present invention, instead of counting 60 seconds at a predetermined time, 60 seconds ± error adjustment seconds are counted and the minute display is advanced by 1 minute. Can be delayed or advanced on a regular basis. Therefore, it is not necessary to adjust the time in a short cycle (once or twice a month) as in the conventional case, and the time adjustment cycle can be significantly lengthened.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a schematic block diagram of an embodiment of a control timepiece device of the present invention. In the figure, 1 is a timer built into the computer. The timer 1 outputs a clock signal based on a pulse signal output from an oscillator such as a crystal oscillator included in the computer. The clock signal output from the timer is generally output at a cycle of 1 second. This clock signal is counted by the counting means 2 to count the progress of 1 second and 1 minute. When the counting means 2 counts the pulses of the clock signal for 1 second, it counts 1 second and outputs 1 second of counting completion to the clock means 3,
When counting the pulses of the clock signal for 60 seconds, the clock means 3 outputs the completion of counting for 1 minute. The counting means 2 is configured such that the count number of the clock signal for one minute can be changed by an external change command.

The clock means 3 updates the time memory every time the counting means 2 counts 1 second and 1 minute, and sequentially changes the display of the time display means 4 composed of a liquid crystal display panel or the like. Since the time stored in the time memory is used as the time used for the control, it can be seen from the control point of view that the time is displayed in the time memory.

The feature of this embodiment is that the error adjustment second setting means 5 is provided.
And the error adjustment count changing means 6 are provided.
The error adjustment second setting means 5 is composed of a switch such as a dip switch, and sets the error adjustment second α for adjusting the delay or advance amount based on the error of the oscillator of the timer 1 in units of seconds. The error adjustment second α set by the error adjustment second setting means 5 is input to the error adjustment count changing means 6. The error adjusting count changing means 6 of the counting means 2 performs the counting of 60 seconds ± error adjusting seconds α minutes instead of causing the counting means 2 to count the clock signal for 60 seconds at a predetermined time. Change the setting of the count number. For example, when counting 1 minute from 23:58, 60
Second ± error adjustment Seconds α minutes are counted. This makes it possible to automatically automatically adjust the time delay or time advance of the error adjustment seconds α. In this embodiment, the time is displayed in seconds,
Of course, the time may be displayed in minutes. The counting means 2, most of the timepiece means 3 and the error adjusting count changing means 6 of the above embodiment can be realized by using a computer. It should be noted that, in this figure, illustration of other means naturally included as a timepiece such as time adjusting means is omitted. Therefore, the first time adjustment or the like is carried out by the time adjusting means (not shown) as in the conventional case.

FIG. 2 shows an example of a software algorithm used in one embodiment when the present invention is implemented by software using a computer. Note that this algorithm displays time in minutes. In this algorithm, immediately after starting, in step ST1, a setting process is performed in which the number of seconds in one minute until the next interrupt (request for timekeeping process) is applied is 60 seconds. That is, an interrupt is made every 60 seconds to perform the timekeeping process of the one-minute clock. In step ST2, it is detected how many seconds the error adjustment second α is set, and the error adjustment second α is stored. Next, in step ST3, it is determined whether or not there is a request (interrupt) for the timekeeping process, and if there is no request for the timekeeping process, the process proceeds to step ST8. When there is a request (interruption) for the timekeeping process, the process proceeds to step ST4, where it is determined whether the time of the clock is a predetermined time (specific time) set in advance. Go to ST6 and set the number of seconds per minute until the next interrupt is 60
Set to seconds. Then, in step ST7, the clock time is set to 1
The time is advanced by one minute (that is, the memory content of the minute is advanced by one minute), and at the same time, the time display of the clock is changed (step ST8). After that, this process is repeated until the specific time is detected in step ST4.

When the specific time is detected in step ST4, the process proceeds to step ST5, and the number of seconds until the next interrupt is applied is increased or decreased by the set error adjustment second α. That is, the setting change process is performed so that an interrupt occurs after 60 seconds ± error adjustment seconds α. As a result, the next interrupt occurs after 60 seconds ± error adjustment seconds α, 60 seconds ± error adjustment seconds α advance the clock time by 1 minute, and the error adjustment is automatically performed. After that, until the specific time is detected in step ST4, an interrupt is taken every 60 seconds to advance the display of the minutes. The whole algorithm constitutes an error adjusting means.

The error adjustment second α is set using the same means as the error adjustment second setting means 5 in the embodiment of FIG. When the set value is changed, the change in the error adjustment second α is stored in step ST2.

[0015]

According to the present invention, instead of counting 60 seconds at a predetermined time, 60 seconds ± error adjustment seconds are counted and the setting is made to advance the minute display by 1 minute. The time display can be periodically delayed or advanced by the error adjustment seconds, and there is no need to adjust the time in a short cycle (once or twice a month) as in the past, so the time adjustment cycle can be changed. It has the advantage that it can be significantly lengthened.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing an example of a software algorithm for operating a computer used in one embodiment when the present invention is implemented using a computer.

[Explanation of symbols]

 1 Timer 2 Counting Means 3 Clocking Means 4 Time Displaying Means 5 Error Adjusting Second Setting Means 6 Error Adjusting Count Changing Means

Claims (1)

[Claims] 1. A control timepiece device configured to use a timer built into a computer to advance the minute display by one minute every 60 seconds counted by the output of the timer. An error adjusting second setting means for setting a second and an error adjusting means for advancing the minute display by 1 minute when counting 60 seconds ± the error adjusting second instead of counting 60 seconds at a predetermined time. Characteristic control clock device.