JPS6018956B2 - Electronic clock regulation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a regulating device for an electronic timepiece that operates in connection with time regulating operations and has rate adjustment means.

In recent timekeeping equipment, the oscillation frequency of the crystal oscillator is used as the time standard to maintain high accuracy, and it is recognized that it is extremely remarkable. Elements such as resistors, capacitors, etc. undergo minute constant changes due to environmental temperature or changes over time, and it is inevitable that the oscillation frequency will shift as a result. In particular, in the case of 24-inch portable watches that use a crystal oscillator, in consideration of the mass production of small crystal oscillator clocks, they can be put to practical use even when the temperature coefficient is relatively large and changes over time cannot be ignored. The reality is that this is the case. In such a case, the user can easily correct the display error of the clock by pressing the push button in time with the time signal, the display value will instantly return to 0, and the timekeeping function will resume from there. It is a well-known fact that fog return function devices are in practical use.

However, in conventional zero return function devices of this type, the timekeeping rate (referred to as rate in watches) is not changed at all, and after a few days, the deviation is accumulated again and the user is He used to complain of having to continue this zero-returning process for hours on end. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and provide a regulating device for an electronic timepiece that corrects the rate when adjusting the drop rate and prevents a large deviation in the rate setting value that occurs when replacing the battery. This is because, in an electronic timepiece having a reference oscillator, a time display means, an electronic circuit means for driving the time display means, and a regulation device for zeroing a second counter, the regulation device includes a frequency variable means, a It has a frequency setting means for setting the frequency of the frequency variable means, a correction switch for controlling the frequency setting means, and an initial condition setting switch. It is characterized in that it is modified according to the information and is reset to a predetermined initial value by operating an initial condition setting switch. An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an electronic timepiece equipped with an electronic regulating device according to the present invention, and the configuration will be explained below.

Reference numeral 1 indicates a standard oscillator using a crystal oscillator as a time reference, and reference numeral 2 indicates a variable frequency divider, which is a frequency variable means, which adjusts the frequency division ratio according to the regulation amount and regulation direction at the corrected zero return time of the electronic clock. and generate a corrected 1-second period timing pulse ◇.

3 is a time counter, seconds counter 4, minute force counter 5.
, an hour counter 6, which counts the time pulses ◇ and supplies a time signal to the display section 7.

Reference numeral 8 denotes a determination circuit that determines the information content when the second counter 4 is corrected to return to zero, and generates a regulation direction signal Sp and a regulation amount signal St.

Reference numeral 9 denotes a frequency division ratio storage circuit as frequency setting means, which sets and stores the frequency division ratio of the variable frequency divider 2 according to the signals Sp and St from the determination circuit 8.

1 This is an AND gate for the carry signal, and is opened and closed by the regulation direction signal Sp of the determination circuit 8 via the inverter 11.

Reference numeral 12 denotes a correction switch, which is opened and closed by an external operation unit (not shown).

13 is a differentiating circuit which differentiates the closing signal of the correction switch 12 and generates a correction pulse Ps.

This correction pulse Ps acts on the second counter 4 as a reset signal, and acts on the component force counter 5 as an AND gate 10.
It becomes a carry signal through the divider ratio storage circuit 9.
acts as a frequency division switching signal. 14 is a switch for initial condition setting, and the closing signal of this switch 14 is converted into a pulse by a differentiating circuit 15, and a frequency division ratio storage circuit is used so that the frequency division ratio of the variable frequency divider 2 becomes the center value of the variable range. Set.

No. FIG. 2 is a detailed diagram of the determination circuit 8 shown in FIG.
The determination circuit 8 is composed of a regulation amount discriminator 16 and condition setting OR gates 17, 18, 19, 20, and the regulation amount discriminator 16 determines the rank according to the regulation amount according to the information content of the second counter 4. Attach. In this example, (
0 to 9) seconds are rank A, (10 to 19) seconds are rank B, (20 to 29) seconds are rank C, and (30 to 39) seconds are rank D.
Rank, (40 to 49) seconds to E rank, (50 to 59)
Seconds are ranked F. In this embodiment, since the range of zero return correction is determined in advance by ±3, the above-mentioned ranks are such that A, B, and C represent the adjustment amounts in the advancing direction, and D,
E and F represent the regulation amount in the delay direction. Therefore, the regulation direction signal Sp, which is the output of the OR gate 17 which inputs the rank signals of A, B, and C, becomes logic "1" when the rate of the clock is in the forward direction, and when the rate is in the backward direction. becomes logic “0”.

Also, the output signal of the OR gate 18 which inputs the rank signals of A and F represents the regulation amount of S time (0 to 9) seconds, and similarly the output signal of the OR gate 19 represents the regulation amount of S time (10 to 19) seconds. , and the output signal St3 of the OR gate 20 is
29) represents the standard amount of seconds, front St, . St2, St3
This constitutes the regulation amount signal St. FIG. 3 is a detailed diagram of the frequency division ratio storage circuit 9 shown in FIG.
23 and three A that control the input conditions to each reversible counter.
The step of the first reversible counter 21 is composed of ND gates 24, 25, and 26, and the step of the first reversible counter 21 is controlled by the variable frequency divider 2 so as to give the minimum variation Δt, to the period of the clock pulse.
The frequency division ratio of the variable frequency divider 2 is changed so that one step of the second reversible counter 22 gives a larger change amount Δt2 to the period of the timing pulse J than the previous period Δt. Furthermore, one step of the third reversible counter 23 is a timing pulse? The variable frequency divider 2 The frequency division ratio is set.

Further, the frequency division ratio switching pulse Ps is applied to the input terminals 1, 12, 13 of each reversible counter via AND gates 24, 25, 26, respectively, and the AND gate 24
is opened and closed by the regulation signal SL' of the determination circuit 8,
Similarly, the AND gate 25 outputs the regulation amount signal St2, AN
The D gate 26 is opened and closed by the regulation amount signal S.

Furthermore, operation designation terminals P, , P2, P3 of each reversible counter
The regulation direction signal Sp of the determination circuit 8 is added to the regulation direction signal Sp, and when the regulation direction signal Sp is logic "1", each reversible counter performs an addition operation and performs one step by the frequency division ratio switching pulse Ps. and add △ to the period of the clock pulse J.
The frequency division ratio is set as the amount of change in t is added, and when the regulation direction signal Sp is logic "0", each reversible counter performs a subtraction operation, and one step is subtracted by the frequency division ratio switching pulse Ps. , the frequency division ratio is set so that the amount of change in Δt is subtracted from the period of the clock pulse 0. Note that when the reset pulse PR is applied by the initial condition setting switch to the reset terminals R, , R2, and R3 of each reversible counter,
The output signals Q, , Q2, and Q3 of each reversible counter set the frequency division ratio of the variable frequency divider 2 to the center value of the variable range.

Furthermore, each reversible counter can perform digit conversion with the upper digit of the valley through the carrier terminal C.

In this embodiment, the correction switch 12 and the differentiating circuit 1
3, judgment circuit 3, inverter 11, AND gate 1 0
1 constitutes a time adjustment device, the determination circuit 8 and the frequency division ratio storage circuit 9 constitute rate correction means, and the time adjustment device and rate correction means constitute an electronic adjustment device. Next, the correcting operation of the fin clock in the above configuration will be explained. The standard output signal of the standard oscillator 1 is frequency-divided by a variable frequency divider 2 operating at a frequency division ratio set by a frequency division ratio storage circuit 9, and becomes a timing pulse J having a period of one second.

The time counter 3 performs a time measurement operation using the time measurement pulse ◇ as a drive signal, and displays the time by moving the display section 7. Further, the information content of the second counter 4, which constitutes the time counter 3, is guided by a discrimination circuit 8 to a minute ratio storage circuit 9 as a regulation direction signal Sp and a regulation amount signal St, as shown in FIG. . Further, the regulation direction signal Sp is connected to an AND gate 101 via an inverter 1.

Now, in order to correct the clock, when the user pushes the correction switch 12 for a certain period of time in accordance with the time signal, a correction pulse P is generated by the differentiating circuit 13.
s is added to the frequency division ratio storage circuit 9 and passes through the AND gate designated by the regulation amount signal St from the determination circuit 8 among the three AND gates 24, 25, 26 shown in FIG. Then, a reversible counter of a digit corresponding to the regulation amount is changed by one step, and a minute change Δt is given to the cycle of the clock pulse, thereby correcting the rate of the clock. The operation of the reversible counter is addition or subtraction depending on the polarity of the regulation direction signal Sp.

This corrected frequency division ratio is stored in the frequency division ratio storage circuit 9 until the next correction pulse is applied.

Further, the correction pulse Ps is such that the regulation direction signal Sp is a logic "
0'', that is, only when the clock has an error in the backward direction, when the clock passes through the AND gate 10 and adds 1 to the component force wanton 5, the second counter 4 returns to zero, and the clock is in the forward direction. If there is an error, the time of the clock is corrected by only resetting the second counter 4 without adding 1 to the component force counter 5.

Note that if the clock is replaced with a battery or the like, the division ratio memory circuit 9
If you temporarily lose the memory of the reset pulse PR, operate the initial condition setting switch 14 to reset the reset pulse PR.
By generating this and setting the frequency division ratio of the variable divider 2 to the center value of the variable range, it is possible to prevent large and medium deviations in rate.

FIG. 4 shows a comparison of the effects of the present invention and the case of only time adjustment in terms of cumulative error. Ps is the correction pulse A, and B is the cumulative error of only time adjustment. In both cases, the horizontal axis is time, and the vertical axes of A and B indicate the integrated error. A highly accurate rate can be obtained.

In this embodiment, switching of the division ratio by the variable frequency divider 2 is used as a means for giving a minute change Δt to the period of the clock pulse J, but as another method, the division ratio memory described above may be used. Another effective method is to convert the output of the circuit 9 into a DC voltage using a DA converter and change the oscillation frequency of the voltage controlled oscillator.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the electronic timepiece according to the present invention, and FIG.
The figure is a detailed diagram of the determination circuit in Figure 1, and Figure 3 is a detailed diagram of the determination circuit in Figure 1.
FIG. 4, which is a detailed diagram of the frequency division ratio storage circuit in the figure, is a waveform chart showing a comparison of the effect on the integrated error between the case of only time adjustment and the present invention. 1...Standard oscillator, 2...Variable frequency divider, 3...Time counter, 4...Second counter, 5...Component force counter, 7 ...Display section, 8.
. . . Judgment circuit, 9 . . . Division ratio storage circuit, 12
. . . Correction switch, 16 . . . Regulation amount discriminator, 21, 22, 23 . . . Reversible counter. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. In an electronic watch having a reference oscillation circuit, a time counter that counts time pulses to generate time information, and a time display means, a frequency variable means for adjusting the period of the time pulse, and a frequency of the frequency variable means. a frequency setting means for setting the second counter; a correction switch for supplying a zero correction signal to a second counter constituting the time counter and a frequency switching signal to the frequency setting means; a frequency setting means for setting a frequency according to information of the second counter; A regulating device for an electronic timepiece, comprising: a determination circuit for supplying a regulation signal to a frequency setting means; and an initial condition setting means for supplying a setting signal for setting a frequency setting means to a predetermined initial value.