JPS585396B2 - densid cay - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing method for an electronic timepiece having a relatively high frequency time standard.

An object of the present invention is to provide a method that allows a user to easily adjust the speed of a watch without having to stop it during use.

Another object of the present invention is to provide a method for automatically adjusting the speed of a quartz watch without using a precise measuring device.

Conventionally, clock shops have been responsible for adjusting the speed of high-precision watches, and consumers have not been able to freely adjust the speed.

This is partly because a unique measuring device was used to measure the clock's speed.

Especially for electronic watches that use a crystal oscillator as the time standard,
In order to adjust the speed using the conventional adjustment method, a highly stable period measuring device is required, and most watch specialty stores do not yet have this type of measuring device.

Therefore, even if the crystal resonator undergoes a frequency shift due to impact or aging, it is difficult to readjust it.

Furthermore, the frequency of a crystal oscillator will fluctuate more or less when the battery voltage fluctuates, and the accuracy of the clock will differ between immediately after replacing the battery and after a year has passed, so consumers may want to adjust the frequency themselves.

The present invention improves these conventional drawbacks and provides consumers with an electronic timepiece that can be easily adjusted.

That is, the gist of the present invention is that a person who wants to speed up or slow down gives the length of a unit time to the watch as information.

As an example, if you start the clock at exactly 7 o'clock on the clock and set it up again at exactly 7 o'clock on the next day and start it again, the clock will be given the absolute length of 24 hours, or 86,400 seconds, as information. They are trying to use this to speed up and slow down the standard signal inside the watch.

Since it can be guaranteed that the manual variation of humans is less than about 0.3 seconds, it is quite possible to reduce the variation to about 0.5 seconds per day.

By employing such a method, the manufacturing precision of the crystal itself may be poor, which provides a great advantage in manufacturing the crystal resonator.

Hereinafter, the present invention will be described in detail based on the drawings.

FIG. 1 shows one of the time standard circuits used in the electronic timepiece of the present invention.
This is an example.

1 in FIG. 1 is a crystal resonator, and 2 is an oscillation circuit.

3 is a 1/2 frequency divider circuit, 4 is an inverter, 5 is a flip-flop with data input, 6 is a 1/2 frequency divider circuit, 7 is an Exc
The lusive OR circuit 8 is a multistage frequency dividing circuit.

If the output signal of the oscillation circuit 2 has the voltage waveform shown in FIG. 31, the output voltage of the frequency dividing circuit 3 becomes the signal shown in FIG. 32.

Furthermore, since the flip-flop 5 performs a delay operation, the output signal becomes as shown in FIG. 33.

Since this signal 33 is the Q output of the flip-flop 5, 34 signals can be obtained by dividing the Q output.

This is the output of the frequency divider circuit 6.

If the output of the OR circuit 10 is at a high level, the output of the AND circuit 9 is the same as the output of the frequency divider circuit 6.
e Since it is transmitted to OR7, at this time Exclusi
The output of ve OR7 becomes a signal like 35 in FIG. 3, which has twice the number of pulses as signal 32.

The signal 36 is the output signal of the AND circuit 11, and is input to the subtraction counter 12.

When the output of the subtraction counter 12 becomes 0, the output of the OR circuit 10 becomes a low level, and the output of the exclusive OR 7 becomes the same as the signal 32, so that no double pulse is generated.

That is, since double pulses are generated until the subtraction counter 12 reaches 0, the number of pulses per second increases accordingly, and the period of the standard signal appearing at the terminal 30 becomes shorter.

Flip-flops 22 and 23 perform a differential operation every time a voltage output appears at the terminal 30 and input a control pulse to the gate 19.

In other words, since the flip-flop 23 is always reset by the oscillation circuit output, it generates a pulse of half the cycle of the signal 31.

At this time, the information regarding the acceleration/deceleration amount stored in the memory circuit 18 is transmitted to the subtraction counter 12 through the gate 19, and from that moment on, the function of generating a double pulse is operated again.

For example, if the multi-stage frequency divider circuit 8 is configured so that the output signal of the terminal 30 is a 1-second signal, a slowing/acceleration effect will work for each 1-second signal, and a 1-second signal with the correct period will always be obtained.

The subtraction counter 12 and gate 19 can be constructed from well-known presettable counters.

Now, we will explain how to find the amount of acceleration, in this case the amount of advancement.

The output of the frequency dividing circuit 3 is always counted by the counting circuits 13, 14, and 15.

When the externally provided switch 29 is pressed, a differential operation is performed by the D flip-flop 24.degree.

If the count value of the counting circuit 15 is a predetermined value, AND
The output of the circuit 20 is at a high level, and in this state A
The signal from the ND circuit 27 passes through the AND circuit 21 and is sent to gate 1.
Added to 7.

The output of a distribution circuit 16 which calculates a predetermined speed/speed amount from the count value of the clock circuit 14 is input to a memory circuit 18 and stored therein.

Subsequently, an output is generated in the AND circuit 28 and the counting circuits 13 and 14
．． 15 is reset.

That is, if the switch 29 is pressed at 7 p.m. on the 11th time with the time signal on the television, the output of the AND circuit 20 is at a low level at this time, so the memory is not changed and only the counting circuit is reset.

If the switch 29 is pressed again at the time signal of 7:00 pm the next day, the output of the AND circuit 20 is at a high level, and the adjustment amount is memorized and then reset.

In other words, the AND circuit 20 may be configured to output a high level from, for example, 10 minutes before to 10 minutes after 24 hours.

This 24 hour period can be set arbitrarily, for example, for one week or one day.
You can decide on time.

An appropriate forbidden band is created by the AND circuit 20 so that the forbidden gate will operate if the device is not used as originally designed.

The time required to pass through the forbidden zone may be determined by taking into consideration the balance of accuracy of the crystal resonator 1.

The time standard circuit of FIG. 1 becomes an all-electronic clock when connected to the digital display circuit of FIG. 5, and becomes a mechanical crystal clock when connected to a step motor drive circuit.

The embodiment shown in FIG. 1 has a function to advance and adjust when the crystal oscillation circuit output is delayed.
To adjust the delay when the progress is in the opposite direction, use the AND circuit 9
Change the NANDAND circuit to Exclusive OR
7 can be replaced with an AND circuit.

In order to be able to correct both lead and lag, it is sufficient to combine both circuits, provide a separate circuit for determining lead or lag, and configure one of them to operate.

The number of stages of the counting circuit 13 is determined from the minimum unit of the adjustment amount.

The output of the counting circuit 14 is sent to a distribution circuit 16 that calculates the amount of slowing and slowing.
Therefore, the smaller the period of the output signal of the counting circuit 13, the more precise the acceleration/slowing amount can be calculated.

As an example, the output of the counting circuit 13 is 4Hz, that is, the period is 0.
Let us assume that the period is 25 seconds and the output frequency of the crystal oscillation circuit is 65536Hz.

As shown in FIG. 2, the number of stages of the counting circuit 14 is six.

In other words, it is assumed that the crystal itself cannot go out of order by 0.25 seconds x 2' = 16 seconds per day.

If the crystal deviation is even greater, the number of stages in the counting circuit 14 must be increased.

If you count 4Hz signals for 24 hours, 86400X4=3
45,600, so when the daily difference of this crystal is exactly 0, the count value of the counting circuit 14.15 becomes the value shown in FIG.

If the upper nine digits of the counting circuit 15 are taken out and the inhibition gate output is taken out, a pass band of about 4 minutes can be obtained.

Of course, at this time, it goes without saying that the digit that has a value of O among the nine digits is outputted to 1 through an inverter and then input to the AND circuit 20.

By the way, when the crystal is delayed, that is, when the period of the output frequency of the crystal oscillation circuit is slow, the count value of the counting circuit 14 does not become 0 as shown in FIG.

If this count value is less than n, for example, how many output signals of the frequency divider circuit 3 should be increased per second can be determined by the following equation.

Here f.

is the frequency of the output of the frequency divider circuit 3, and X is the number of increasing pulses per second.

In other words, in the method shown in Figure 1, when one pulse is increased,
Even if the time is 33 KHz, there will not be a large error, so the X-shape n15 is obtained.

It can be seen that the distribution circuit 16 can be constructed by creating a decoder that outputs a binary output of n15 in response to a binary input of -0.

However, if the frequency of the signal to be corrected is low, minute corrections cannot be made.

FIG. 4 shows the counting circuit 14, distribution circuit 16, gate 17, and memory circuit 18 when the frequency of the signal to be corrected is 327,680 Hz, which is 10 times the upper frequency, and the correction method is to vary the division ratio as described later. This is an illustration.

In this case, the speed is calculated as 0.95n.

That is, it is sufficient to output a binary output of 0.95n for a binary input of -n.

In FIG. 4, 37 to 42 represent the counting circuit 14;
3 to 48 are inverters, and 49 to 56 are M circuits.

Although 64 AND circuits are actually required, they are omitted for the sake of simplification of the drawing.

57-62 are OR circuits, 63 is an AND circuit, 64 is an inverter, 65 is an AND circuit, and 66-71 is a memory circuit 18.

That is, input to the memory circuits 66-71 is performed by applying a signal to the set/reset terminal.

Although the wiring of the OR circuits 57 to 62 is not yet completed in FIG. 4, it will be easily understood.

To add more information to FIG. 1, the oscillation circuit 2 and the frequency dividing circuit 3 must not be stopped even when setting the time of the clock.

FIG. 5 shows a display section and a decoder circuit when configuring a digital display electronic timepiece using a liquid crystal or LED.
2 is a 1/10 frequency divider circuit, 73 is an IA frequency divider circuit, 74 is 1
/10 frequency divider circuit, 75 is 1/6 frequency divider circuit, 76 is 1/1
0 frequency division circuit, and 77 is a 1/2 frequency division circuit.

This allows the display of hours to seconds.

For example, the output shown in FIG. 1 is connected to the frequency dividing circuit 72.

78 to 83 are decoders for performing seven-element display, and 84 to 89 are display bodies.

FIG. 6 shows another embodiment of the present invention, which is different from the speed control method shown in FIG.

Here, 90 is a frequency dividing circuit with a variable frequency division ratio, and this frequency division ratio is determined based on information in the memory circuit 91.

92 is a gate, and 93 is a division circuit.

That is, in this case, even if the time information from the outside is not 24 hours, even if it is 24XM (M is a positive integer), the deviation per 24 hours can be calculated by dividing the deviation by M.

This way of thinking can be applied, for example, to calculating the deviation per hour.

A multiplication circuit 94 is used in place of the distribution circuit shown in FIG.

This output is input to the memory circuit 91 through the gate 95.

In the example shown in FIG. 6, if the frequency dividing ratio changes by 1, the frequency is adjusted by the period of the input signal of the frequency dividing circuit 90.

As detailed above, the electronic timepiece of the present invention is very advantageous for high-precision timepieces such as quartz wristwatches because the user simply inputs the time information and the time is automatically adjusted. This also has the advantage that there is no problem even if there are manufacturing variations in the crystal itself.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of a time standard circuit used in the electronic timepiece of the present invention. 1... Crystal resonator, 2... Oscillation circuit,
3...1/2 frequency divider circuit, 7-...Exclu
sive OR circuit, 8...Multi-stage frequency dividing circuit, 1
3,14.15... Counting circuit, 16...
・Distribution circuit, 18...Memory circuit, 12...
...Subtraction counter, 29...External switch. FIG. 2 is a binary table for explaining the function of the counting circuit. FIG. 3 is a signal waveform diagram of each part for explaining the operation of FIG. 1. FIG. 4 is an example of a distribution circuit that takes out an input of -0 as an output of 0.95n. 37-42... Counting circuit, 49-56...
...AND circuit, 57-62...OR circuit, 6
6-71...Memory circuit. FIG. 5 shows the circuit configuration of the digital display section. 72.74.76...1/10 frequency divider circuit, 73
゜75...1/6 frequency divider circuit, 77...
1/2 frequency divider circuit, 78-83...Decoder, 8
4-89...Digital display. FIG. 6 shows another embodiment of the time standard circuit used in the electronic timepiece of the present invention. 90... Frequency dividing circuit with variable division ratio, 91...
...Memory circuit, 93...Division circuit, 94
・・・・・・Multiplication circuit.

Claims (1)

[Scope of Claims] 1. Standard signal generating means for generating a time standard signal of a constant period, frequency dividing means with a variable division ratio for dividing the time standard signal, counting means for counting the standard signal, and a constant time period. It is composed of an external operation switch for inputting the length of the pulse as information from the outside, a means for comparing the information of the certain period of time with the count contents of the counting means to calculate a slowing/slowing amount, a memory means for storing the slowing/slowing amount, and a display means. , the electronic timepiece is characterized in that the frequency division ratio is determined based on the speed and speed values stored in the memory means, and a prohibition gate is provided so that the external operation switch is effectively operated only at a predetermined time. . 2 Standard signal generation means for generating a time standard signal of a constant period; frequency dividing means for dividing this time standard signal with a variable division ratio; counting means for counting the standard signal; an external operation switch input as information; a means for comparing the information of the certain period of time with the count content of the counting means to calculate a slowing/slowing amount; a memory means for storing the slowing/slowing amount;
It is composed of a display means and a division means for dividing the contents of the counting means by the predetermined time, and a signal based on the value calculated by the division means is stored in the memory means, and a signal based on the value stored in the memory means is used. An electronic timepiece characterized in that the frequency division ratio is determined.