JPH07306277A - Clock mechanism - Google Patents

Abstract

PURPOSE:To provide a clock mechanism being employed in an information processor in which the accuracy is enhanced by resetting the time freely while reflecting the reset time gradually. CONSTITUTION:The clock mechanism comprises a time counter 1 for counting the input clock to display the time, a time information input means 2, means 3 for calculating the time error based on the difference between input time information and the content of the time counter 1, and means 4 for distributing the time error generate a corrected time series sequentially being set in the time counter 1. A clock control means for increasing/decreasing the number of clock pulses being inputted to the time counter 1 for a designated period according to an error direction flag carrying the sign of error and the value thereof, may be substituted for the corrected time setting means 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timepiece mechanism used in an information processing device.

[0002]

2. Description of the Related Art Generally, an information processing apparatus has a clock mechanism inside, and the clock mechanism provides a system time display function, a system automatic operation function, a system billing function, a performance measurement function, and the like.

Since there is an error in the clock mechanism, a difference from the actual time occurs, which causes a problem that the start time of automatic operation deviates from the actual time. To compensate for this, means are provided for manually or automatically resetting the time.

FIG. 7 is an explanatory view of the prior art of a timepiece mechanism. The time counter 1 counts clock pulses and displays the value as time. The processor 11 can know the time by reading the contents. The time is corrected by the processor 11 writing to the time counter 1 using the time input.

However, the resetting causes the time to become discontinuous, and in the worst case, a time that does not exist may be created, or the time may be reversed or the same time may occur twice. Therefore, after regularly stopping the system, It was necessary to reset the time, or in a 24-hour non-stop system or the like, reset the time in consideration of the state where the job was not operating.

[0006]

Therefore, there has been a problem that there is a limitation in correcting an error of the timepiece mechanism and it is troublesome.

An object of the present invention is to make it possible to freely reset the time by gradually reflecting the reset time, and also to realize a timepiece mechanism with improved accuracy. .

[0008]

1 to 3 show the principle of the present invention. First invention: As shown in FIG. 1, a timepiece mechanism of the present invention includes a time counter 1 for displaying time by counting input clock pulses, a time input means 2 for inputting time information, and an input. Based on the difference between the displayed time information and the display time of the time counter 1 at that time, the time until the correct time is determined, the error calculation means 3 for calculating the time error up to that time, and the time error are calculated. Correction time setting means 4 for dividing and distributing and sequentially generating correction time sequences from the display time to the correct time and setting them in the time counter 1.
Have and.

Second invention: As shown in FIG. 2, the time counter 1 and the time input means 2 are the same as in the first invention. The error calculating means 3 calculates a time error with a sign based on the difference between the input time information and the display time of the time counter 1 at that time, and calculates the corresponding number of clocks. Further, instead of the correction time setting means 4 of the first invention, an error counter 5 that holds the number of clocks corresponding to the time error and counts down for each correction operation, an error direction flag 6 that holds the sign of the error, and an instruction For a period of
Clock control means 7 is provided for increasing / decreasing the number of clock pulses input to the time counter 1 according to the value of the error direction flag 6.

Third Invention: As shown in FIG. 3, the timepiece mechanism of the present invention includes a time counter 1 for displaying time by counting input clock pulses and a time input means 2 for inputting time information. Based on the previous time holding means 21 that holds the input time, the input time, the held time, and the time displayed by the time counter 1, the time counter 1 is assigned with a sign. The error rate calculation means 31 for calculating the reciprocal of the error rate, the error rate register 32 for holding the reciprocal of the error rate, the error direction flag 6 for holding the sign of the error, and the clock pulse as the value of the error rate register 32. Correction counter 51 that counts up to and error rate register 32
Of the number of clock pulses input to the time counter 1 and the comparator 33 that detects that the value of the counter and the value of the correction counter 51 coincide with each other. Increase / decrease according to the value of direction flag 6
Clock control means 7 for reducing the clock frequency.

[0011]

The time counter 1 counts the clock pulses to display the elapsed time with the period of the clock pulse as the minimum unit (resolution). If the time is set so that the time is displayed, the time is displayed. The time is set by the time input means 2. It is also used to correct erroneous times.

First invention: When the time information is input, the error calculating means 3 calculates the difference between the time information and the display time of the time counter 1. And the correct time (Note:
The time until it is set is set, and the time error up to that point is calculated.

The correction time setting means 4 sequentially generates a correction time sequence from the display time to the correct time using the time difference of a predetermined minimum unit that does not affect the system clock of the information processing apparatus as a correction amount and sequentially generates the time counter. Set to. For example, the time of the above-mentioned correction amount is added to the first display time and set in the time counter 1 as the correction time, and the time of the next correction time is set by adding the time of the correction amount to the time counter 1
Is set to the number of times to eliminate the time error.

By doing so, the display time can be corrected while maintaining continuity and monotonic increase. Second invention: The present invention corrects the time by increasing / decreasing the number of clock pulses instead of directly writing the correction time into the time counter 1 as in the first invention.

When the time information is input, the error calculating means 3 calculates the difference between the time information and the display time of the time counter 1. Although this is a time error in a narrow sense, it is desirable to calculate the time error in consideration of the time required for the correction operation described later. Further, the time error is converted into the number of corresponding clock pulses and set in the error counter 5. The sign of the error is set in the error direction flag 6. The error counter 5 first holds the number of clock pulses corresponding to the time error, and counts down according to the correction operation.
The correction operation is performed until the error counter 5 becomes zero.

The clock control means 7 includes an error direction flag 6
Indicates that the time error is positive, that is, when the time counter 1 is delayed, the clock pulse is generated even in the middle of the cycle of the normal state to increase the count speed of the time counter 1 and the error direction flag 6 is set. When the time error is negative, that is, when the time counter 1 is advancing, the count speed of the time counter 1 is slowed by suppressing the clock pulse.

With this configuration, the display time can be corrected while maintaining continuity and monotonic increase. Third invention: Unlike the second invention, the present invention increases the accuracy of the timepiece mechanism by increasing / decreasing the number of clock pulses to be given to the time counter 1 by an amount corresponding to the error rate from the normal state.

When a new time is input, the error rate calculation means 31 determines the error of the time counter 1 according to the time, the time held in the previous time holding means 21 and the time of the time counter 1. The rate is calculated and the reciprocal thereof is set in the error rate register. The correction counter 51 counts clock pulses, and the comparator 33 uses the error rate register 32
When it is detected that the contents of the correction counter 51 and
The clock control means 7 is notified as a correction instruction. The clock control means 7 increases / decreases the number of clock pulses by 1 according to the correction instruction and the sign of the error of the error direction flag 6, as in the second aspect of the invention. The correction counter 51 is reset and starts the next counting. Further, the input time is held in the previous time holding means 21 and used for the next correction.

With this configuration, the clock is incremented or decremented by 1 each time the number of reciprocals of the error rate is generated, so that the clock is corrected by the error rate.
If there is no fluctuation in the error rate, the accuracy will be kept high.

[0020]

FIG. 4 is a block diagram of an embodiment of the first invention of the present invention. FIG. 5 is a block diagram of an embodiment of the second invention. FIG. 6 is a block diagram of an embodiment of the third invention. The same functions as those in FIG. 1 are designated by the same reference numerals.

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 4, the clock mechanism is mainly composed of a time counter 1 which displays the time by counting clock pulses input at a constant cycle.
The time input routine 2 which is on 10 and controls the processor 11 to input the time information, and when the time information is input,
An error calculation routine that calculates the difference between the time information and the display time of the time counter 1, determines the period until the correct time (note: not the input time), and calculates the time error up to that point 3 and time error are divided and distributed,
Correction time setting routine 4 for sequentially generating correction time sequences from the display time to the correct time and setting them in the time counter 1
And consists of.

The processor 11 may be the processor of the information processing device or another microprocessor.
In the case of manual input, the time input routine 2 accepts the previously input time data as the correct time by the timing input entered by the operator in consideration of the timing, and passes it to the error calculation routine 3. Also, as automatic input,
It is also possible to generate a correct time judged from the timing input such as a time signal that occurs periodically and the upper part of the display time of the time counter 1 at that time and pass it to the error calculation routine 3.

The error calculation routine 3 calculates the difference between the input correct time data and the current time obtained by reading the contents of the time counter 1. Then, set the period until the correct time (note: it is not the entered time),
Calculate the number of corrections for dividing and distributing the total of the signed time error and the period until the correct time is set as the correction amount, which is the minimum unit time difference that does not affect the system clock of the information processing device. . The correction amount for one time may be determined according to the resolution required by the information processing device.

Here, the period until the correct time is set may be a predetermined value, but it is better to change it according to the amount of error. For example, the error amount is set to 100 times.
In particular, in the case of a lead error, it is necessary to take a long period of time because it is necessary to correct the contents of the time counter 1 that has already advanced without reversing the time.

The correction time setting routine 4 resets the value obtained by sequentially adding the correction amount to the time counter 1 at regular intervals. By repeating this for the number of times of correction described above, the correction time series from the display time to the correct time is sequentially generated and set, and the time can be corrected while maintaining continuity and monotonicity. When the content of the time counter 1 is ahead of the actual time, means for stopping the time counter during correction (which can be easily realized by an AND gate and FF configured to suppress clock input) is provided. However, if there is no correction, there is no problem if the correction period is long.

An embodiment of the second invention will be described with reference to FIG. The present embodiment is an example in which the time correction described above is realized by hardware (clock control circuit). The error calculating means 3 calculates the time error, sets the number of clocks of the time corresponding to the time required for the error and the correction operation in the error counter 5, and sets the sign of the time error in the error direction flag 6. To do. The error counter 5 counts down for each subsequent correction operation.

The clock control circuit 7 divides the source clock pulse having a short cycle by the frequency dividing counter 70 to generate an appropriate clock pulse as an input of the time counter 1. A decoding circuit 71 that decodes the frequency division counter to generate a signal generated in each cycle, a decoding circuit 72 that generates a signal generated in the middle of the cycle, and a selector (multiplexer circuit) 73 that selects / suppresses them. And a clock pulse is generated by the AND gate 74 which takes the logical sum of the output and the source clock pulse. In the normal state, the division counter 70
The time counter 1 is operated by a clock pulse having a constant cycle obtained by selecting a signal generated for each cycle of 1 and the AND with the source clock pulse.

While the zero detection circuit 55 detects that the value of the error counter 5 is not zero, the clock pulse input to the time counter 1 by controlling the selector 73 every cycle of the frequency division counter 70. If the content of the error direction flag 6 is '0' (delay correction: clock pulse added), the clock pulse is generated by 1 by selecting the signal generated in the frequency dividing counter 70. Then, the value of the error counter 5 is counted down by the increased number of clock pulses, and the process is repeated until the value of the error counter 5 becomes zero. That is, the count speed of the time counter is doubled to catch up with the actual time. Error direction flag 6
If the content is 1 (advance correction: clock pulse reduction), the clock pulse is suppressed by also suppressing the signal generated in each cycle of the frequency division counter 70. That is, in this case, the time counter 1 is stopped and waiting for the actual time to catch up. As a result, the time can be corrected while maintaining the continuity of the time. Note that if the correction operation is performed every N cycles of the frequency dividing counter 70, the correction is performed gently, and the linearity of the time change is improved.

The time input means 2 and the error calculation means 3 are
As in the embodiment of the present invention, it may be performed by software using a memory and a processor, but it is obvious that it may be implemented by a hardware circuit.

An embodiment of the third invention will be described with reference to FIG. The present embodiment is an example in which a timepiece mechanism is realized in which the accuracy is increased by increasing / decreasing the number of clock pulses given to the time counter 1 by an amount corresponding to the error rate.

The input time is set and held in the input register 22. At that time, the time previously input and held is transferred to the previous time holding register 21. The error rate calculation unit 31 obtains a time error by taking the difference between the value of the input register 22 and the value of the time counter 1, and obtains the time difference by the difference between the values of the input register 22 and the previous time holding register 21, The error rate is obtained by dividing the error by the time difference. further,
Calculate the reciprocal of the error rate. At this time, the value of the input register 22 is simultaneously set in the time counter 1 and corrected to the correct time.

The error rate calculator 31 sets the reciprocal of the calculated error rate in the error rate register 32, and sets the sign of the error in the error direction flag 6. The clock control circuit 7 is the same as that of the second embodiment of the invention.

The correction counter 51 counts clock pulses, the value of the correction counter 51 and the value of the error rate register 32 are compared by the comparator 33, and when they match, the correction flag 56 is set and the correction counter 51 is set. Is reset.

When the correction flag 56 is set, the clock control circuit 7 increases / decreases the number of clock pulses input to the time counter according to the contents of the error direction flag 6.

The above registers, counters, etc. are connected to the bus of the processor (microprocessor) and can be controlled by the program of the processor. Further, the error rate calculation unit 31 is realized by a program.

A specific example of accuracy correction will be described below.
The frequency dividing counter 70 is a counter that counts the source clock pulse of 1 MHz, and wraps around when the value reaches 1000, at which time one signal is output from the decoding circuit 71. This outputs one clock pulse through the selector 73 and the AND gate 74. That is, this output is 1 KHz
Clock output. The time counter 1 is this 1 KHz
The clock is counted and the time is displayed. Therefore, 1
A clock with a resolution of mS.

The error rate calculator 31 compares the input time information with the time read from the time counter 1.
As a result, when the error rate is 1/10000 and there is a delay (need to be corrected in the forward direction), the reciprocal of the error rate of 10,000 is set in the error rate register 32, and the error direction flag 6 is set. Set to "1". When the correction counter 51 that counts the 1 KHz clock matches the content of the error rate register 32 (10,000 in this case), the correction flag 56
Is set. The clock control circuit 7 performs a correction operation when this flag is set. If the error direction flag 6 is "1", the value of the frequency division counter 70 is 1000.
In addition to the above time, the selector 73 is controlled so as to output the clock pulse at the time of reaching 500. This gives 1 /
Since the number of clocks input to the time counter 1 increases with an accuracy of 10,000, the accuracy of the time counter 1, that is, the timepiece mechanism is corrected.

Similarly, when the error rate is 2 / 10,000 and there is a lead (need to be corrected in the delay direction), the reciprocal 5,000 of the error rate is set in the error rate register 32, and the error direction is set. The flag 6 is set to "0". The content of the correction counter 51 that counts the 1 KHz clock is the error rate register.
When it matches the contents of 32 (5,000 in this case), the correction flag 56 is set, and the clock control circuit 7 sets the value of the frequency division counter 70 to 1 when the error direction flag 6 is "0".
It is suppressed so that the clock pulse is not output at 000 (of course, at 500). This gives 10,
Since two of the 000 clock pulses are suppressed, the number of clock pulses input to the time counter 1 is reduced at a rate of 2/1000, and the accuracy is corrected.

When the second invention and the third invention are applied at the same time, the correct time input according to the second invention is set in the time counter 1 and then the error of the source clock according to the third invention is set. It will operate while correcting the tendency. Therefore, the operation of directly setting the input time in the time counter 1 described in the third embodiment of the invention is unnecessary.

As a result, the timepiece mechanism can be kept highly accurate.

[0041]

As described above, according to the first and second aspects of the present invention, by gradually reflecting the reset time, the time can be reset freely.
According to the third aspect, the accuracy of the timepiece mechanism can be improved.

[Brief description of drawings]

FIG. 1 is a principle diagram of a first invention.

FIG. 2 is a principle diagram of the second invention.

FIG. 3 is a principle diagram of a third invention.

FIG. 4 is a block configuration diagram of an embodiment of the first invention.

FIG. 5 is a block diagram of an embodiment of the second invention.

FIG. 6 is a block configuration diagram of an embodiment of the third invention.

FIG. 7 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 1 time counter 2 time input means (time input routine) 21 previous time holding means 22 input register 3 error calculation means (error calculation routine) 31 error rate calculation means (error rate calculation section) 32 error rate register 33 comparator 4 corrected time Setting means (correction time setting routine) 5 Error counter 51 Correction counter 55 Zero detection circuit 56 Correction flag 6 Error direction flag 7 Clock control means (clock control circuit) 70 Dividing counter 71, 72 Decoding circuit 73 Selector 74 AND gate 10 Memory 11 processor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masao Yamamoto 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Mikayo Wada, 1015, Kamiodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited

Claims (3)

[Claims] 1. A time counter (1) for displaying time by counting input clock pulses, time input means (2) for inputting time information, input time information and a time counter at that time. Based on the difference from the display time of (1), the period until the correct time is determined, the error calculation means (3) for calculating the time error up to that time, and the time error are divided and distributed, and displayed. A timepiece mechanism having a correction time setting means (4) for sequentially generating a correction time sequence from a time to a correct time and setting the correction time sequence in the time counter (1). 2. A time counter (1) for displaying time by counting clock pulses input, time input means (2) for inputting time information, input time information and a time counter at that time. An error calculation means (3) for calculating a time error with a sign based on the difference from the display time of (1) and calculating the corresponding number of clocks.
An error counter (5) that holds the number of clocks corresponding to the time error and counts down for each correction operation, an error direction flag (6) that holds the sign of the error, and a specified period,
A clock mechanism having clock control means (7) for increasing / decreasing the number of clock pulses input to the time counter (1) according to the value of the error direction flag (6). 3. A time counter (1) for displaying time by counting input clock pulses, a time input means (2) for inputting time information, and a previous time for holding the input time. Holding means (21)
Error rate calculation means for calculating the reciprocal of the signed error rate of the time counter (1) based on the input time, the held time, and the time displayed by the time counter (1) ( 31), an error rate register (32) that holds the reciprocal of the error rate, an error direction flag (6) that holds the sign of the error, and a correction counter that counts clock pulses until the value of the error rate register (32) is reached. (51), the comparator (33) that detects that the value of the error rate register (32) and the value of the correction counter (51) match, and the number of clock pulses input to the time counter (1)
The number of clock pulses input to the time counter (1) is increased / decreased according to the value of the error direction flag (6) during a specified period.
A clock mechanism having a clock control means (7) for reducing the clock.