JPH0334111B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method of operating a microcomputer, and particularly to a 4-bit microcomputer that is convenient for use in electronic watches.

(b) Prior Art Conventional electronic clock circuits have been based on a frequency division method based on the counter configuration, but this has had the inconvenience of requiring the design to be redone from the beginning when specifications are changed. Therefore, CPU-based electronic clocks using microcomputers have been put into practical use.

In general, CPU-type electronic clocks have the advantage of being able to change specifications by simply changing the mask of the ROM that stores the program, but the timekeeping operation counts the number of program steps based on the processing time of one program. The program is complicated because it performs addition processing, and since the CPU is constantly operating at high speed, the current consumption is significantly higher than that of conventional frequency division electronic clocks, which significantly shortens battery life. However, it was unsuitable for clocks, wristwatches, etc. that use batteries as a power source.

Conventionally, microcomputers that stop operating have been devised in order to reduce current consumption. In such systems, after system clock generation is stopped, interrupts are disabled until operation is restarted, or if an interrupt occurs while operation is stopped, the program counter is reset. , the operation starts from the first address of the program. Therefore, the operation of the program stops in the middle of the program, and it is not possible to accept an interrupt or proceed with the program in the stopped state, resulting in a drawback that there are many restrictions on program creation.

(c) Purpose of the Invention The present invention has been made in view of the above points, and when an interrupt occurs while the operation is stopped, the stack retains the address of the stop instruction that caused the operation to stop. By enabling interrupts during normal operation, interrupts when operation is stopped, and restarting execution of the next program when operation starts, it is possible to simplify the creation of programs including stop instructions and to minimize current consumption. The purpose is to provide a microcomputer that can perform the following functions.

(d) Structure of the Invention The present invention provides a reference signal generation circuit and a stop signal that controls the stop of the operation of generating a clock signal for controlling the operation of the system using the output of the reference signal generation circuit. The start is an interrupt signal,
and a clock generator controlled by an operation start signal generated based on internal or external factors, a ROM in which instructions constituting the program are written, and the above-mentioned clock generator for retrieving the instructions written in the ROM. a program counter that specifies the address of the ROM; a stack that stores the incremented address of the program counter from which the instruction executed at the time of the interrupt was read to hold the return address after interrupt processing; The clock generator is controlled by a control circuit that decodes the read instruction and generates a control signal for executing the instruction, and a signal from the control circuit to which the operation stop instruction is applied. In a microcomputer equipped with a state control circuit that outputs a stop signal to the clock generator to stop its operation, the control circuit performs the following in response to an interrupt that occurs during operation.
The incremented address of the program counter is held in the stack, and after the interrupt processing is completed, the address held in the stack is set in the program counter to advance the program and respond to an interrupt that occurs while the operation is stopped. On the other hand, the control circuit causes the address of the program counter that read the stop instruction that caused the operation to stop to be held in the stack without incrementing it, and after the interrupt ends, the address held in the stack is transferred to the program counter. By setting the counter, the stop command that caused the operation to stop is executed again to stop the operation, and when the operation is started by the operation start signal generated after the operation is stopped, the program counter is incremented. The feature is that the program proceeds from the specified address.

(E) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention, which includes a reference signal generation circuit 1, a clock generator 2, a switch input circuit 3, a state control circuit 4, a timer counter 5, and a chronograph counter. 6,
ROM7, program counter 8, stack 9,
Instruction register 10, control circuit 1
1. This is a microcomputer for an electronic watch, which is composed of an ALU 12, an ACC 13, a RAM 14, a decoder 15, and a latch circuit 16.

The reference signal generation circuit 1 oscillates a signal with a frequency determined by a crystal oscillator 17 connected to an external terminal, regardless of whether the system is in operation or not, which will be described later, and further divides the frequency of the signal. A predetermined frequency-divided signal is supplied to a clock generator 2, a switch input circuit 3, a timer counter 5, a chronograph counter 6, and the like. Further, the reference frequency generating circuit 1 outputs an interrupt signal INT2 for performing a time counting operation every fixed period of time, for example, every 0.5 seconds, regardless of whether the system is operating or not.

The clock generator 2 generates a system clock signal for operating the CPU based on the divided signal applied from the reference frequency generating circuit 1 and supplies it to each section. A stop signal CLKSTOP for stopping the clock signal generation operation is applied from the state control circuit 4 to the clock generator 2, and interrupt signals INT0, 1, 2, 3 and a timer are output.
TIMEROUT and operation start signal
CLKSTART is applied and these signals restart the stopped operation.

Switch input circuit 3 has external terminals M ₁ to M ₄ and S ₁
~ _S4 , which prevents the switches connected to each external terminal from chattering and captures switch opening/closing data, and the data is sent to each data bus DB. Especially external terminals S ₁ ~ _{S 4}
The opening/closing of the switch connected to can be specified by the switch control signal SWCON of the state control circuit 4, and the operation start signal CLKSTAT can be output depending on the opening/closing of the specified switch. Furthermore, an interrupt signal INT3 can be output by closing a switch connected to external terminals _S1 to _S4 . In the chronograph mode, a chronograph control signal CHRCON is output which controls the start, lap and stop of the chronograph counter 6 by opening and closing the switches connected to terminals _S1 and _S2 .

State control circuit 4 is instruction bus IB
It controls the state of each circuit in various modes, and controls the switch control signal SWCON that controls the switch input circuit 3, the reset and start of the timer counter 5, and the timer time. A stop signal that also stops the timer control signal TIMCON, which performs selection, etc., and the operation of the clock generator 2.
Output CLKSTOP etc. Furthermore, an external terminal LAMP for connecting a lamp and an external terminal ALM for connecting to an alarm sound generator are provided.

Timer counter 5 is the instruction bus
The timer time can be set depending on the program sent to the IB, and if the state control circuit 4 instructs to start the timer,
The reference frequency signal output from the reference signal generation circuit 1 is counted regardless of whether the system is in operation or stopped, and when the set timer time elapses, the signal TIMEROUT is output. Furthermore, interrupt
When the timer is instructed to start with INT0 generation set, an interrupt signal is periodically generated.
Output INT0.

The chronograph counter 6 is a counter that counts pulses of 1/100 seconds, and while the chronograph is starting, it outputs an interrupt signal INT1 every 1/10 second, regardless of whether the system is in operation or stopped. In addition, the count contents of the chronograph counter 6 are sent to the decoder 15 via the chronograph data bus CDB.
is applied to

The ROM 7 consists of 1392 x 14 bits, in which programs for timekeeping operations and control of various parts are written in a fixed manner. An instruction code consisting of the following is output to the instruction register 10. The instruction register 10 stores the instruction code output from the ROM 7 and is connected to the instruction bus.
Output to IB. After processing one instruction, the program counter 8 receives the next address or jump control signal and outputs the jump destination address signal.
Output to ROM7. Stack 9 has a capacity of 8 levels, and when proceeding to interrupt processing or a subroutine, the contents of program counter 8 are set to 1.
The added value is memorized. However, after the instruction "SCP" to stop the operation of the clock generator 2 is executed, when interrupt processing is performed, the contents of the program counter 8 are stored as they are in the stack 9, and after the interrupt processing is completed, the clock is restarted. The stop command “SCP” is executed.

The RAM 14 consists of 84×4 bits, and data such as current time, alarm time, timer time, etc. is stored in a predetermined area. The address of the RAM 14 is specified by an instruction, and the data stored at the specified address is sent to the data bus DB, or the data sent to the data bus DB is specified by a send command or a write command. The address is saved. The ALU 12 inputs the data sent to the data bus DB, performs processing such as addition and subtraction, stores the results in the ACC 13, and sends the data to the data bus DB again.

The decoder 15 and the latch circuit 16 constitute a display circuit, and the decoder 15 converts the applied 4-bit data into 7 segment signals for display and outputs them to the segment bus SB. Latch circuit 1
Reference numeral 6 stores and holds the segment signals output to the segment bus SB and outputs them to external terminals a to g, and there are as many as the number of display elements. Which latch circuit 16 is to store the converted segment signal is specified by the program. For example, when converting the data of the first digit of the second of the current time, the latch circuit 16 stores the converted segment signal. The latch circuit 16 corresponding to the display element on which the digit is to be displayed is specified by the program. On the other hand, in addition to the data bus DB, the output chronograph data bus CDB from the chronograph counter 6 is applied to the decoder 15, and either the data bus DB or the chronograph data bus CDB can be switched and selected depending on the program.

The control circuit 11 decodes the instructions from the ROM 7 sent to the instruction bus IB and controls each circuit using the system clock output from the clock generator 2 in order to perform the operation corresponding to the instruction. and further interrupt signal
Program counter 8 performs processing corresponding to the interrupt when INT0, 1, 2, or 3 is output.
and controls ROM7. That is, the control circuit 11
In the normal operating state, the program advances the program by sequentially adding 1 to the contents of the program counter 8, and if an interrupt occurs in the operating state, the program counter 8 at that time is
The value obtained by adding 1 to the contents of is stored in stack 9, and the addresses corresponding to interrupt signals INT0, 1, 2, and 3 are set in program counter 8. When the interrupt processing is completed, the value stored in stack 9 is stored. By setting the program counter 8 again, the program is controlled to advance in sequence. On the other hand, if the clock generator 2 restarts due to a factor other than an interrupt while the clock generator 2 has stopped operating due to the execution of the clock stop instruction "SCP", then The contents held in the program counter 8,
In other words, 1 is added to the value specifying the address where the clock stop instruction "SCP" that caused the operation to stop is stored, and the program proceeds.
When an interrupt occurs, the contents of the program counter 8 at that time are stored as they are in the stack 9, the addresses corresponding to the interrupt signals INT0, 1, 2, and 3 are set in the program counter 8, and the contents are stored after the interrupt processing is completed. By setting the value stored in the stack 9 in the program counter 8, the clock stop command "SCP" is executed again, and the program counter 8 is controlled so that the operation of the clock generator 2 is stopped.

FIG. 2 is a circuit diagram of clock generator 2 shown in FIG. The counter 18 has a configuration in which three stages of flip-flops are connected, and the output of each stage is
T ₁ , T ₂ , ₂ , T ₃ , ₃ are taken out and NORed accordingly
Connected to gates 19-22. Further, the divided output φ1 from the reference signal generation circuit 1 is applied to the input terminal IN of the counter 18 via the NOR gate 23.NOR gates 24 and 25 constitute a flip-flop, and the output of the NOR gate 24 is
applied to the NOR gate 23 and the OR gate 26,
The output of OR gate 26 is applied to reset terminal R of counter 18. The NOR gate 25 receives a stop signal output from the state control circuit 4.
CLKSTOP is applied, and the NOR gate 24 receives interrupt signals INT0, 1, 2, 3 and an operation start signal.
CLKSTART, timer output TIMEROUT, and an initial signal MR that is output when power is applied are applied. Initial signal MR is OR gate 26
is also applied. The output of NOR gate 23,
Output _T1 of counter 18 and NOR gates 19-2
The output of 2 is the clock to operate the system.
Output as CLK1-6.

When the initial signal MR is applied when power is applied, the counter 18 and the flip-flop are reset. Therefore, the output of the NOR gate 24 becomes "0", the divided signal .phi.1 is applied to the counter 18 via the NOR gate 23, the counter 18 starts operating, and the system clocks CLK1-6 are output. On the other hand, when the operation stop command “SCP” is executed, a stop signal is output from the state control circuit 4.
The flip-flop is set by CLKSTOP, and the output of NOR gate 24 becomes "1", so counter 18 is reset, and NOR gate 23
cuts off the divided output φ1. Therefore, system clocks CLK1 to CLK6 are no longer output, and the system operation is stopped. An interrupt signal INT0 is generated when the reference signal generation circuit 1 operates even when the system operation is stopped.
INT1, INT2 and timer output
Interrupt signal generated according to TIMEROUT or key switch signal input externally
The flip-flop is reset by the output of either INT3 or operation start signal CLKSTART.
The output of the NOR gate 24 becomes "0". Therefore, the counter 18 starts operating again, system clocks CLK1-6 are outputted, and the system starts operating. However, if the operation starts with interrupt signals INT0, 1, 2, and 3, the stop command "SCP" is executed again after the interrupt processing is completed, and the stop signal
Operation stops again because CLKSTOP is output. Therefore, only necessary operations are performed, and operations are stopped in other cases.

3 and 4 are flowcharts showing examples of programs written to the ROM 7, and the second
The figure shows the main program, and FIG. 3 shows the interrupt processing program. The operation will be explained using FIGS. 3 and 4.

First, when power is applied, initial clear is activated, each circuit is reset, and the program counter 8 is reset.
specifies address 0 of ROM7. Starting from address 0, a program for initial settings is written.
By executing this program, "0" or predetermined data is stored in the RAM 14 and initial settings are made. Next, a mode change program is executed. This program is switch input circuit 3
Data indicating whether the switch is open or closed is transferred from the data bus.
Input via DB, and depending on the content of the data, determine whether current time mode, alarm mode, timer mode or chronograph mode is selected, and if other functions are provided, which mode is selected. Determine whether each mode is a correction mode and check the RAM corresponding to each mode.
Set the flag in 14. Then, a predetermined address of the ROM 7 in which the selected program is written is specified, and the program jumps there. In this example, mode selection is performed using external terminals _M1 to _M4.
and the switches connected to the external terminals S 1 to S ₄ (these switches are referred to as MS ₁ to _{MS 4} and SW ₄ , respectively), and the switches connected to the external terminals S ₁ to _{S 3} (these switches are referred to as SW ₁ to _{SW 3} , respectively). It is programmed to perform corrections, turn on lamps, and silence alarms. However, by changing the program, it is possible to use two to four arbitrary switches to select a mode or perform other operations.

In the current time mode, the current time is first displayed. This displays the seconds, minutes, hours, months, etc. stored in each digit at a predetermined address in the RAM 14, depending on the display command that allows address specification of the RAM 14.
The day and day of the week are sequentially addressed and the data is sent to the data bus DB. and decoder 15
The converted segment signal is stored in the latch circuit 16 to be displayed. At this time, the decoder 15 is controlled in advance by a command so that the data bus DB is connected. In particular, in the case of hour display, it is determined whether 12-hour display or 24-hour display is selected, the ALU 12 performs processing appropriate for the display according to the program, and the result is applied to the decoder 15. to be displayed. On the other hand, in the case of displaying the day of the week, the function of the decoder 15 is switched according to a command for converting the day of the week, and then data on the day of the week is applied. Since the latch circuit 16 continues to output the stored segment signal to the external terminals a to g until the next new segment data is rewritten, a display is made even if the clock generator 2 stops operating.

After the display is performed as described above, RAM1
4, which indicates whether the mode is in correction mode or not, and if it is in normal display mode, the switch is turned on.
Closing SW ₁ , if in correction mode, switch SW ₁ ~
Set the closure of ₃ . That is, upon execution of this command, the state control circuit 4 outputs the switch control signal SWCON, controls the switch input circuit 3, and performs the specified operation of the specified switch, that is, closing switch SW ₁ or switching switches SW ₁ to _3. Control is performed so that the operation start signal CLKSTART is output only when the closing is performed. When the switch settings are completed, a command "SCP" for stopping the operation of the clock generator 2 is executed. When this instruction code is sent to the instruction bus IB and applied to the state control circuit 4, the state control circuit 4 sends a stop signal.
Output CLKSTOP and clock generator 2
Set the flip-flop inside. By setting this flip-flop, the divided signal from the reference signal generating circuit 1 is cut off, and generation of the system clock is stopped. Therefore, the execution of the program does not proceed to the next step with the stop command "SCP", and all operations based on the program are stopped. Therefore, during this time, the current flowing through the system is drastically reduced.

The clock generator 2 starts operating again when a specified switch is activated, when an interrupt request INT0, 1, 2, or 3 is received, or when the timer counter 5 counts up. , the flip-flops of clock generator 2 are reset by these signals. In the case of an interrupt, the operation of the clock generator 2 starts, but the contents of the program counter 8, that is, the contents that address the stop instruction "SCP" are stored in the stack 9.
The address indicating the interrupt processing program shown in FIG. 4 is set in the program counter 8. When the interrupt processing is completed, the address saved in the stack 9 is set in the program counter 8, so the stop instruction "SCP" is executed again and the operation is stopped. On the other hand, when the specified switch operation is performed, the switch input circuit 3 outputs the operation start signal CLKSTART, and when the timer counter 5 counts up, the timer output is output.
Output TIMEROUT. These outputs reset the flip-flop of clock generator 2 to resume operation and the program proceeds to the next step.

The next program checks the mode change flag in the RAM 14 and determines whether there is a mode change request. If a mode change is requested, the program jumps to the mode change program described above, and if there is no request, the program proceeds to the next program. The mode change flag is set or reset by interrupt processing INT0. As will be described later, INT0 periodically checks the states of switches MS ₁ to MS ₄ and SW ₄ for selecting the mode, sets the flag to "1" and starts the timer counter 5 if the mode is to be changed. Therefore, when a mode change is requested, the timer output TIMEROUT is used to operate the clock generator 2 to perform the mode change.

On the other hand, if there is no mode change request, it means that the specified switch has been operated, and the next program will determine whether it is in the correction mode or not and which of switches SW ₁ to _{SW 3} has been closed. It makes a judgment and performs the processing corresponding to the operation. For example, when switch SW ₁ is closed in the normal mode, a command to turn on the lamp is executed, the external terminal LAMP of the state control circuit 11 is set to "1", and the next command specifies opening of switch SW ₁ and the clock is turned on. Executes the stop command “SCP”. When the switch _SW1 is opened, the operation starts again as described above, the command to turn off the lamp is executed, and the program jumps to the switch setting program again. Further, when the switch _SW1 is closed in the correction mode, the second data stored in the RAM 14 is rewritten to "0". At this time, it is determined whether it is 29 seconds or 30 seconds, and if it is 30 seconds or more, the folding process is performed. When switch SW ₂ or switch SW ₃ is closed, the hour or minute in RAM 14 is transferred to ALU 12, incremented by 1, and again.
Write to RAM14. Furthermore, if switch SW ₂ or SW ₃ continues to be closed, fast forward correction is performed. In this case as well, the switch operation is designated and the clock operation stop command "SCP" is used.
That is, the timer counter 5 is set to 1 second and started, and after designating the opening of switches SW ₂ and SW ₃ , the stop command "SCP" is executed. Therefore, clock generator 2 starts operating at the switch.
This is the case when SW ₂ or SW ₃ is opened and the timer counter 5 counts 1 second, and it is determined whether switch SW ₂ or SW ₃ has been closed for a certain period of time by determining in the program after the operation starts. can be determined, and if it is closed, add 1 to the hour or minute in RAM 14 and then write it to timer counter 5.
Set 250ms and jump to the program that specifies opening of switches SW ₂ and SW ₃ again. As a result, the values are added and fast-forwarded every 250 ms until switch SW ₂ or SW ₃ is opened. When the correction program performs the process of resetting seconds and adding minutes or hours, the data corrected by the display command is immediately sent to the data bus DB and displayed. When switches SW ₂ and SW ₃ are opened, the program jumps from the modification program to the switch setting program described above.

Alarm mode, timer mode, and chronograph mode are also programmed in the same pattern as the current time mode described above.

When in alarm mode, depending on the display command
The data at the address where the alarm time is stored in the RAM 14 is sequentially designated and displayed digit by digit. The switch can be specified in alarm setting mode.
Specify the closing of SW ₁ to ₃ , specify the closing of switch SW ₁ in alarm display mode, and execute the operation stop command “SCP”. If there is no mode change request and the specified switch is closed, the program proceeds to alarm time setting, display and lamp blinking programs. In the alarm mode, when switch SW ₁ is closed, the lamp lighting command, switch SW ₁ open designation, and operation stop command "SCP" are executed even in the alarm setting mode, and after the operation starts, the lamp extinguishing command is executed. Depending on the situation, the lamp is turned on and off. On the other hand, when the switch SW ₂ or SW ₃ is closed, the mode is the alarm time setting mode, and the minute or hour of the alarm time is set. This program uses the same program as the current time correction program, and uses the addition process as a subroutine to memorize the hour or minute of the alarm time.
Program it to specify the address of RAM14. Of course, the set contents are immediately displayed by a display command.

In the timer mode, the timer time display program, switch setting program, and operation stop command "SCP" are similarly executed in sequence. In this case, the timer is not timer counter 5, but RAM
It is a timer with seconds, minutes, and hours stored in 14. The display command therefore addresses a timer in RAM 14. In the timer mode, there is no correction mode, and when setting the switch, it is determined whether or not to generate an alarm sound, and when the alarm sound is to be generated, switches SW ₁ to _{SW 3} are set to close.
When the alarm sound does not occur, only set switch SW ₁ to close. If the operation resumes and there is no mode change, the program proceeds to the timer time setting, display, start, stop and lamp flashing programs. If the mode does not generate an alarm sound when the switch SW ₁ is closed, the lamp is turned on and off using the lamp blinking program in the same way as in the current time mode and alarm mode. On the other hand, switch SW ₂ or
When SW ₃ is closed, the minutes or hours are corrected by the correction program. Also, when switch SW ₁ is closed in a mode that generates an alarm sound, a flag for starting the timer is set in the RAM 14 if the timer is set, and nothing is done if the timer is not set. Jump to the switch setting without doing so.

The chronograph display in chronograph mode is
1/10 second of the chronograph time in RAM14, second,
The minutes and hours are displayed sequentially using the display command, and the data bus
1/100 of the chronograph counter 6 by switching the chronograph data bus CDB to the decoder 15 with a switching command between DB and the chronograph data bus CDB.
Second data is displayed. Directly applying 1/100 second data to the decoder 15 in this way would require a long processing time and would not be able to track 1/100 second data, which would result in inaccurate data display. This is because it cannot be displayed.

In the switch setting, switches SW ₁ and ₂ are set to close. When switch SW ₁ or ₂ is closed, the operation starts and the program advances, but in the case of chronograph mode, the chronograph control signal is sent from the switch input circuit 3 regardless of the program.
CHRCON is output and controls the chronograph counter 6. That is, the flip-flop that generates start and stop in the chronograph counter 6 is set or reset by the chronograph control signal CHRCON outputted when switch SW ₁ is closed, and the chronograph control signal CHRCON outputted when switch SW ₂ is closed. Signal CHRCON sets or resets the lap flag flip-flop for displaying 1/100 second laps.

On the other hand, the program checks the flip-flops in the chronograph counter 6 and the flip-flops for the wrap flag to see if the chronograph counter 6 has started or is in the wrap state, and sets the chrono stop flag and wrap flag in the RAM 14. Or reset. Further, when the switch SW ₂ is closed and the wrap flag is set while the chronograph counter 6 is in the reset state, the chronograph data in the RAM 14 is reset. At the end of this program
Display the chronograph data in RAM14 using the display command and jump to the switch setting. Incidentally, addition processing is performed on the chronograph data in the RAM 14 according to the interrupt signal INT1 output from the chronograph counter 6 every 1/100.

The interrupt processing INT0 shown in FIG. 4 takes a certain period of time, for example, every 62.5 ms, and samples the switches MS ₁ to MS ₄ and SW ₄ .
That is, the data of the switches MS ₁ to MS ₄ and SW ₄ are inputted from the switch input circuit 3, stored in the RAM 14, and compared with the data sampled last time. If there is no change as a result, reset the mode change flag in RAM 14 and return to the main program; if there is a change, set the mode change flag and timer counter 5 to 32ms, start it, and return. do.

Interrupt processing INT1 is chronograph counter 6
It takes every 1/10 second when is starting. This process adds 1 to the 1/10 second data of the chronograph data in RAM 14, and if there is a carry, it is carried to the chronograph second data, and if there is a carry, it is carried to the upper digit, and so on. . Next, if the chronograph mode is not in the lap state, the chronograph data is displayed using a display command and the process returns to the main program.

Interrupt processing INT2 is generated from the reference signal generation circuit 1 every 1/2 second, and performs timekeeping processing and the like. First, the data of the 1/2 second flag in the RAM 14 is taken into the ALU 12 and 1 is added to it, and it is determined whether the result is "1" or "2". If it is "1", it returns to the main program. “2”
In this case, set "0" to the 1/2 second flag and perform timer processing. Timer processing is executed only when the timer has started. If it has started, 1 is subtracted from the seconds of the timer data in RAM 14, and if there is a borrow, 1 is further added from the upper digit.
Perform borrow processing by subtracting . Also, as a result,
It is determined whether the seconds, minutes, and hours have all become "0", and if they are "0", an alarm sound command is executed and an alarm sound for the timer is output to the external terminal ALM.
Next, 1 is added to the second data of the current time, and if there is a carry, carry processing is performed. If there is a carry to the minute digit in this carry process, alarm processing and snooze processing are performed. In the alarm process, the hour and minute data stored in the RAM 14 and the hour and minute data of the current time after the carry process are extracted for each digit into the ALU 12 and it is determined whether they match. If they match, an alarm sound generation command and an interrupt INT3 set command are executed to enable interrupts from the switch input circuit 3. Snooze processing determines whether there is a snooze request, and if there is a snooze request,
Add 1 to the snooze data in RAM14,
When the result is a predetermined time, for example, 5 minutes, the alarm sound generation command and interrupt INT3 set command are executed again. Next, it is determined whether the mode flag in the RAM 14 is the current time mode, and if the mode is the current time mode, the new carried current time data is displayed, and if it is another mode, the program returns to the main program.

Interrupt processing INT3 is set to switch input circuit 3 when an alarm sound occurs and switches SW ₁ to
Required when any SW ₄ is closed. This process stops the alarm signal output from the external terminal ALM of the state control circuit 4 with an alarm sound stop command, sets the snooze flag if there is a snooze request, sets the snooze data in the RAM 14, and returns. do. If there is no snooze request, the flashing of the alarm sound mark is stopped, the snooze flag is reset, and the process returns. If interrupt INT3 is set, the specified switch SW ₁ ~
No matter which SW ₄ is operated, only the interrupt signal INT3 is output from the switch input circuit 3, and the switch designation is ignored.

The priority of interrupt processing is INT0, 1, 2, 3.
This order is determined by the control circuit 11. Also, interrupt signals INT0, 1, 2,
3 are connected to set the flip-flops of the control circuit 11, and when interrupts are disabled, the interrupt processing is performed by the set flip-flops after the inhibition is released. Furthermore, if an interrupt occurs while the system clock is stopped, the system clock stop instruction "SCP" is executed again after the interrupt is processed.

(F) Effects of the Invention As described above, according to the present invention, when an interrupt occurs while an operation is stopped, the stack retains the address of the stop instruction that caused the operation to stop, thereby preventing an interrupt during normal operation. By enabling an interrupt when an operation is stopped and restarting execution of the next program when an operation is started, the operation of creating the clock that executes the program can be stopped by using stop commands provided at various places in the program. In addition, after executing the interrupt processing requested while the system is stopped, the system can be stopped again by returning to and executing the instruction that stopped the system, thereby completely eliminating unnecessary system operations. As a result, current consumption is significantly reduced, and programs can be shortened and easily assembled. Therefore, it has the advantage that changes in functions and specifications can be made extremely easily.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram of the clock generator shown in FIG. 1, and FIGS. 3 and 4 are flow diagrams showing example programs. DESCRIPTION OF SYMBOLS 1... Reference signal generation circuit, 2... Clock generator, 3... Switch input circuit, 4... State control circuit, 5... Timer counter, 6... Chronograph counter, 7... ROM, 8... ...Program counter, 9...Stack, 10...Instruction register, 11...Control circuit, 12
...ALU, 13...ACC, 14...RAM, 1
5...Decoder, 16...Latch circuit.

Claims (1)

[Scope of Claims] 1. A reference signal generation circuit, and the stop of the operation of generating a clock signal that controls the operation of the system by the output of the reference signal generation circuit is controlled by a stop signal, and the start of the operation is controlled by an interrupt. A clock generator that is controlled by signals and operation start signals generated based on internal or external factors, and a clock generator in which the instructions that make up the program are written.
a ROM, a program counter that specifies the address of the ROM in order to retrieve an instruction written in the ROM, and a program counter that reads an instruction executed when an interrupt occurs in order to hold a return address after interrupt processing. a stack for storing incremented addresses of the ROM; a control circuit for decoding the instruction read from the ROM and generating a control signal for executing the instruction; and a control circuit to which an operation stop instruction is applied. a state control circuit that outputs a stop signal to the clock generator to stop the operation of the clock generator; On the other hand, the control circuit causes the stack to hold the incremented address of the program counter, and advances the program by setting the address held in the stack in the program counter after the interrupt processing is completed; In response to an interrupt that occurs while the operation is stopped, the control circuit causes the address of the program counter that read the stop instruction that caused the operation to stop to be held in the stack without incrementing it;
After the interrupt ends, the address held in the stack is set in the program counter to cause the stop instruction that caused the stoppage of the operation to be executed again to stop the operation, and the operation start signal generated after the stoppage of the operation is performed. The microcomputer is characterized in that the program counter advances the program from an incremented address when the operation starts.