GB2107494A - Electronic timepiece with microprocessor - Google Patents

Abstract

An electronic timepiece comprises a reference signal generating circuit (1), a clock generator (2) in response to a reference signal for generating a system clock signal and a processor (CPU) operating in response to the system clock signal, the processor including a read only memory (7) in which a program is fixedly written and a random access memory (14) for storing time data. A state control circuit (4) is provided for controlling the clock generator, a switch input circuit (3) and other attached circuits, so that operation of the clock generator is stopped by a predetermined output (CLK STOP) from the state control circuit when a predetermined instruction in the program written in the read only memory is executed. A stop of operation of the clock generator is removed when an interrupt signal (INTO-INT3) is generated. After an interrupt processing the predetermined instruction is executed so that operation of the clock generator is again stopped. The timepiece incorporates alarm, chronograph and timer functions. <IMAGE>

Description

SPECIFICATION Electronic timepiece The present invention generally relates to an electronic timepiece. More particularly, the present invention relates to an electronic timepiece of a so-called central processing unit system using, for example, a 4-bit microcomputer.

A conventional electronic timepiece is generally of a type of a so-called frequency dividing system dividing by a counter high frequency reference signals from a quartz oscillator. In such a conventional electronic timepiece, it is necessary to alter all of the hardware when the specification is changed and thus there is an inconvenience that a further design must be newly done. Then in order to facilitate the change of a specification, an electronic timepiece of a so-called central processing unit system in which a timing operation is controlled by a microcomputer (program) has been proposed and put into practice.

Such an electronic timepiece of a central process sing unit system has the advantage of changing the specification thereof simply by changing a mask of a read only memory in which a program is stored.

However, in a conventional electronic timepiece of a central processing unit system, there is an inconvenience that the consumed electric current is very much large as compared with an electronic timepiece of a prior frequency dividing system. More particularly, while a conventional electronic timepiece of a central processing unit system performs a timing operation in response to a predetermined time period signal (for example, 1 Hz signal) from a timer, a microcomputer is fast operated all the time and thus the operating electric current becomes very large.

On the other hand, one of approaches for implementing a smaller operating electric current in a general microcomputer is an approach utilizing a HALT instruction. However, since such a HALT function stops an operation per se of a reference oscillator, a timing function can not be maintained even if such approach applies to a timepiece without any modification.

Then, one prior art which is interested to the present invention is United States Patent No.

4,224,789, issued to Sasaki et al. on September 30, 1980, entitled "Electronic Timepiece". In this United States Patent No. 4,224,789, although a reference oscillator is continuously operated, a clock generator operates only if a switch for operation is operated or 1 Hz signals are obtained, and during the period other than that, operation of the clock generator is stopped and thus an operation of a central processing unit is stopped. Accordingly, in this cited patent, timing operation is never stopped and an operating electric current intermittently flows, and hence a consumed electric current is made so small. However, the cited patent involves a serious problem to be further solved.More particularly, in this cited patent, although the stop of clock generation is removed by a switching input or a 1 Hz signal, a subsequent necessary processing can not be made unless a central processing unit determine what factor the stop of clock generation is removed by. More particularly, in the cited patent, it is necessary to provide in a main program further steps for determining what the factor is and thus the program becomes complicated.

On the other hand, in a conventional electronic timepiece of a central processing unit system, there is a type making timing operation by counting the number of program steps with reference to processing time for one instruction. Even in such a type, a program becomes longer and complicated.

Accordingly, a principal object of the present invention is to provide an electronic timepiece wherein a consumed electric current can be reduced and a program can be simplified.

An electronic timepiece in accordance with the present invention comprises a clock generator the operation of which is stopped in response to the fact that a predetermined instruction in a program written in a read only memory is executed, the stop of operation of the clock generator being removed when an interrupt is caused.

As described in the foregoing, according to the present invention, the necessity to determine always in a main program a factor by which stop of clock generation is removed since an interrupt is used for removing the stop of operation of the clock generator. Accordingly, a program becomes short and very simple. If and when all of the programs necessary for operating as a timepiece are made to be executed by interrupt operation, respective programs can be made independently of a main program and an extra program for determining a mutual relation between the programs is not needed. Therefore, according to the present invention, an error is hardly generated in making a program and designing of program for a short period becomes possible.

In addition, if and when an operation necessary for a timepiece is made by such an interrupt, an advantage of causing no errors in a timing operation can be obtained as compared with a type making a various determination in a main program such as the above described cited patent. More particularly, although a longer main processing step in the cited patent delays an incrementing processing per a second and thus there is a possibility that an error is caused in a current time, there is no possibility that an error is caused in a current time in accordance with the present invention since an operation necessary for a timepiece can be securely conducted irrespective of process of a main processing program if an operation necessary for a timepiece is achieved by an interrupt.In other words, according to the present invention, no consideration from a program for eliminating counting errors in a current time is needed. This also plays a very important role in simplifying a program.

Thus, according to the present invention, there is a significant advantage that a program is simplified as compared with the above described cited patent. As a matter of course, according to the present invention, it is also possible to reduce a consumed electric current since an operation of a clock generator is intermittently effected.

In a preferred embodiment of the present invention, in case where an interrupt is caused when an operation of the clock generator is being stopped, an original program address is executed again after the interrupt processing and the clock generator is again stopped. In a general microcomputer, it is usual that, after an interrupt processing is executed, a program returns to a program address following an address at the time when the interrupt is caused.In the embodiment of the present invention, in case where an interrupt is caused when a system clock operates and a program has already been executed, a program returns to the next program address after completion of the interrupt processing, and in case where an interrupt is caused when the system clock stops, a program returns back to the same program address after the completion of the interrupt processing and instruction for stopping the operation of the clock generator is executed. In such a way, it is possible to process an interrupt caused when the clock generator is stopped. According to the present embodiment, an extra program for determining whether or not it is necessary to stop the clock is not needed in a main program returning from an interrupt program, and thus an independency between each programs is further enhanced and programming can be more simply made.

In a preferred embodiment of the present invention, a switch input circuit connected to external terminals and accepting switching signals of switches and a state control circuit for controlling the switch input circuit are provided. The switch input circuit can be controlled by the state control circuit so that an interrupt can be made in any state of any switch and only an operation of a particular switch can be effectively handled. The stop of operation of the clock generator is removed in response to an interrupt signal outputted by operation of a switch or a signal outputted by operating of a designated switch.

According to the present embodiment, an interrupt can be made by a switch and an operation of a central processing unit can be restarted only when the designated switch is operated. In addition, since the function of the switch can be arbitrarily set by a program, no restriction is needed in changing a specification and thus a general purpose electronic timepiece can be obtained. More particularly, although a conventional electronic timepiece is adapted such that the function of the switch connected to the external is fixedly determined in accordance with an AND-ORROM and the like and the function can not be set and added by a program, which causes some restrictions in changing a specification and thus is very inconvenient, the present embodiment can entirely avoid such inconvenience.

In a further embodiment of the present invention, an electronic timepiece has a chronograph function.

In this embodiment, the unit of 1/100 second is counted by a chronograph counter and the unit larger than the unit of 1/10 second is accumulated by a random access memory. The count data of the unit of 1/100 second and the count data of the unit larger than the unit of 1/10 second are selectively provided to a display decoder by instructions. According to the preferred embodiment, since the unit of 1/100 second is directly counted by a chronograph counter and displayed and the counting and displaying operation of the unit larger than the unit of 1/10 second are processed by a program, the count of the unit of 1/100 second and the display thereof can be precisely made even if an operation of a microcomputer (CPU) is not so fast.More particularly, in case where a conventional electronic timepiece of a central processing unit system is provided with a chronograph function, a chronograph data is stored in a random access memory and an addition processing is made in the same manner as the above described timing operation. However, the addition processing by a program takes a substantial time and, in addition, if the program for displaying the data is executed, the processing speed of the program cannot follow measurement and display of the unit of 1/100 second and thus only up to the unit of 1/10 second can be obtained. However, the embodiment can avoid such inconvenience. Furthermore, since only the counting operation of the unit larger than the unit of 1/10 second is made to be processed by a program, the embodiment has the advantage of making short and simple the program necessary for a chronograph function.

These objects and other objects, features, aspects and advantages ofthe present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Fig. 1 is a schematic diagram showing one example of an electronic clock as one embodiment of the present invention; Fig. 2 is a block diagram showing the whole structure of one embodiment of the present invention; Fig. 3 is a block diagram showing a reference signal generating circuit and a general timer; Fig. 4 is a circuit diagram showing one example of a clock generator; Fig. 5 is a timing diagram for explaining an operation of the Fig. 4 circuit; Fig. 6 is a circuit showing one example of a switch input circuit; Figs. 7A and 7B are circuit diagrams showing a portion of a state control circuit; Fig. 8 is a circuit showing portions associated with a chronograph circuit; Fig. 9 is a block diagram showing one example of an interrupt control portion included in a control circuit; Fig. 10 is a circuit showing portions associated with a program address; ; Fig. 11 is a timing diagram explaining an operation of the Fig. 10 circuit; Fig. 12 is a diagram showing one example of storage areas of a random access memory; Fig. 13 is a main flow diagram explaining the whole operation of the Fig. 2 embodiment; Fig. 14 is a flow diagram showing a program of INTO; Fig. 15 is a flow diagram showing a program of lNT1; Fig. 16 is a flow diagram showing a program of INT2; Fig. 17 is a flow diagram showing a program of INT3; and Fig. 18 is a flow diagram showing in detail an operation of a chronograph mode.

Fig. 1 is a schematic diagram showing an exterior view of one embodiment of the present invention.

An electronic clock ECK in accordance with the present embodiment comprises first and second numeral displaying areas DA1 and DA2. The first numeral displaying area DA1 can display a numeral of 6 figures and the second numeral displaying area DA2 can display a numeral of 4 figures. Flag segments FS1-FS7 are provided so that a day of the week can be displayed by driving a corresponding segment. A mode displaying area MDA can display one of a plurality of operation modes of the electronic clock ECK. The basic operation modes in this electronic clock comprise a current time displaying mode, an alarm mode, a timer mode and a chronograph mode. An alarm mark segment AMS informs through a driving thereof that an alarm sound will be generated when the alarm time comes.

Now, referring to Fig. 1, it will be described in brief what kind of display is made in each mode. First, in the current time displaying mode, the current time is displayed in the first numeral displaying area DA1 up to the unit of 1 second. In the example as shown, the time of 12 hours 59 minutes 31 seconds is displayed.

The date is displayed in the second numeral displaying area DA2. In the example as shown, the date of December 30 is displayed. Assuming that the date of December 30 is Sunday, the flag segment FS1 would be driven for display. Next, in the alarm mode, the current time is displayed in the first numeral displaying area DA1 and an alarm time is displayed in the second numeral displaying area DA2. Assuming that the example as shown is in the alarm mode, an alarming sound is generated at twelve thirty. At that time, an alarm mark segment AMS is being driven.

Even in this mode, a day of the week is displayed by the flag segments FS1 -FS7. In addition, in the timer mode, a timer time period is displayed in the first numeral displaying area DA1 and that now is timer mode is displayed in the mode displaying area MDA.

In the timer mode, the current time is displayed in the 4 figures of the second numeral displaying area DA2. At that time, the on-and-off of a colon mark included in the second numeral displaying area DA2 can display a pass of the unit of a second. Finally, in the chronograph mode, a passing time period is displayed in the first numeral displaying area DA1 and a current time is displayed in the second numeral displaying area DA2. The mode displaying area MDA displays that now is a chronograph mode.

The unit of 1/100 second is displayed in the least significant digit D1 of the first numeral displaying area DA1 and the unit of 1/10 second is displayed in the digit D2.

The above described displaying manner is merely by way of example and thus it is intended that any modificationed of such displaying manner does not affect the substance of the present invention.

Fig. 2 is a block diagram showing a whole structure of one embodiment of the present invention. Prior to the detailed description, an outline of the whole structure will be described with reference to Fig. 2.

A reference signal generating circuit 1 generates signals of frequency determined by a quartz oscillator 17 and frequency divides the signals to a predetermined frequency divided signals which are applied to a clock generator 2, a switch input circuit 3, a timer counter 5, a chronograph counter 6 and the like. In addition, an interrupt signal INT2 is outputted from the reference frequency signal generating circuit 1 for performing a time counting operation every a predetermined time period, for example, 0.5 second.

The clock generator 2 generates system clock signals for enabling a central processing unit operation by frequency-divided signals applied from the reference frequency generating circuit 1 and supplies the same to each portions. To the clock generator 2 are applied a stop signal CLK STOP for stopping an operation of generation of clock signals from the state control circuit 4, interrupt signals INTO, INT1, INT2 and INT3, a general timer output GTIMER OUT and operation starting signal CLK START, so that an operation of the clock generator 2 being stopped by these signals is restarted.

The switch input circuit 3 comprises external terminals M1-M4 and S1-S4 and accepts switching data of the switches connected to each of external terminals, the data each being sent to a data bus DB.

Particularly, the switching of the switches connected to the external terminals S1-S4 can be designated by a switch control signal SWCON from the state control circuit 4 and an operation starting signal CLK START can be outputted through a switching of the designated switch. Further, the circuit 3 can output an interrupt signal INT3 through a switching of switches connected to the external terminals S1-S4.

In the chronograph mode, a chronograph control signal CHRCON is outputted for controlling the start, lap and stop of the chronograph counter 6 through a switching of switches connected to the terminals S1 and S2.

The state control circuit 4 is controlled by a program fed to an instruction bus IB to control the state of each circuit in each mode. The state control circuit 4 outputs a switch control signal SWCON for controlling the switch input circuit 3, a timer control signal TIMCON for effecting selection and the like of the reset, start and time period for timer of the general timer 5, a stop signal CLK STOP for stopping an operation of the clock generator 2, and the like.

Further, the state control circuit 4 is provided with an external terminal LAMP for connecting lamps and an external terminal ALM connected to an alarm sound generating apparatus.

The general timer 5 can set a time period for timer by a program fed to the instruction bus IB and outputs a signal GTIMER OUT starting operation of the clock generator 2 when the set time period passes.

The chronograph counter 6 is a counter for counting the unit of 1/100 second up to 1/10 second and outputs an interrupt signal INT1 per 1/10 second. The counted content in the chronograph counter 6 is applied to a decoder 15 through a chronograph data bus CDB.

A read only memory (ROM) 7 is comprised of 1390 x 14 bits, for example, and a program for timing operation and controlling of each portions is fixedly written therein. The read only memory 7 outputs to an instruction register 10 an instruction code com prised of 14 bits written in an address designated by a program counter 8 of 11 bits. The instruction register 10 stores the instruction code outputted from the read only memory 7 and outputs the same to the instruction bus IB. Upon completion of the processing of one instruction, the program counter 8 outputs to the read only memory 7 the next address signal or an address signal the address of which is one to be jumped when a jump control signal is received.A stack 9 has a capacity of 8 levels and stores a content which is a result of an addition of the content of the program counter 8 and the number 1 in case where a program is transferred to an interrupt processing or a subroutine. However, in case where an interrupt processing is made after an instruction "SCP" for stopping an operation ofthe clock generator 2 was executed, the content in the program counter 8 is stored in the stack 9 without any change and after completion of an interrupt processing, instruction "SCP" for stop of clock is again addressed and executed.

A random access memory (RAM) 14 is comprised of 84 x 4 bits, for example, and data such as a current time, an alarm time, a timer time period and the like are stored in the predetermined storage areas therein. The random access memory 14 is addressed by instructions. Thus, the random access memory 14 sends out to the data bus DB the data stored in the address addressed by a send instruction, or stores the data sent out to the data bus DB in the address addressed by a write instruction. An arithmetic and logical unit (ALU) 12 receives the data sent out to the data bus DB, makes processing of addition, subtraction and the like, makes the result of the processing be stored in an accumulator (ACC) 13 and again send the same to the data bus DB.

A decoder 15 and a latch circuit 16 structure a displaying circuit, the decoder 15 converting an applied 4-bit data into seven segment signals for display as shown in Fig. 1 so that the seven segment signals are outputted to a segment bus SB. The latch circuit 16 holds the segment signals outputted to the segment bus SB and outputs the same to external terminals a-g, the number of the latch circuit 16 corresponding to the number of display elements.

The latch circuit 16 in which the converted segment signals are to be stored is designated by a program.

For example, if and when the data of the first digit (D1 in the embodiment shown in Fig. 1) of a second of a current time is converted, a latch circuit 16 corresponding to a display element which is to display the first digit of the second is designated by a program. On the other hand, since a chronograph data bus CDB from a chronograph counter 6 as well as the data bus DB is applied to the decoder 15, one of the data bus DB and the chronograph data bus CDB can be selected by a program.

The control circuit 11 decodes the instruction sent out from the read only memory 7 to the instruction bus IB and controls each circuit based on system clocks outputted from the clock generator 2 so that an operation corresponding to the instruction is executed. In addition, the control circuit 11 controls the program counter 8 and the read only memory 7 in such a manner that when interrupt signals INTO, INT1, INT2 and INT3 are outputted, the processing corresponding to the interrupt is done.

The detail of the reference signal generating circuit 1 is shown in Fig. 3. The reference signal generating circuit 1 comprises an oscillating circuit 101 connected to a quartz 17, the reference signals of 32.768 kHz from the oscillating circuit 101 being applied to a frequency dividing circuit 102 of 15 stages. The frequency dividing circuit 102 comprises a combination of well-known flip-flops, the output 1 thereof being applied to a clock generator 2. The outputs 7, 8,8,9,10,11,11,12,12and 13arn applied to a 1/100 second signal generating decoder 103. The 1/100 second signal from the decoder 103 is applied to a chronograph counter 6.The outputs 10 and 814 from the frequency divider 102 are applied to an edge extracting circuit 104 for extracting an edge of a 0.5 second pulse. The circuit 104 comprises a NOR gate 105 and a latch circuit 106. The output 10 is applied to a clock terminal pl of the latch circuit 106 the output Q of which, together with the output 14, is applied to the NOR gate 105. The output per14 is also applied to a latch input L of the latch circuit 106. From the NOR gate 105 in the circuit 104 a pulse is outputted per 0.5 second, the 0.5 sec pulse being applied to a set input S of an R-S flip-flop 107.

Accordingly, from an inverted output Q of the flip-flop 107, an interrupt signal INT2 is outputted per 0.5 second. The interrupt signal INT2 is used for an interrupt processing of timing operation. A signal INT2 RESET is applied to the latch circuit 106 and a reset input R of the flip-flop 107.

The lower portion of the Fig. 3 structures a general timer 5 which outputs a signal INTO for making an interrupt for each predetermined time period and a signal GTIMER OUT indicating the pass of the predetermined time period. The outputs 10 and prll from the frequency divider 102 are applied to a 62.5 m sec pulse providing circuit 109. The circuit 109 comprises a NOR gate 110 and a latch circuit 111 just like the above described circuit 104, the circuit 109 outputting a pulse per 62.5 m sec. The 62.5 m sec pulse is applied to a set input S of an R-S flip-flop 112 and thus an interrupt signal INTO is outputted per 62.5 m sec from a non-inverted output Q of the flip-flop 112. A signal INTO RESET is applied to the latch circuit 111 and a reset input of the flip-flop 112.

A frequency divider 113 of seven stages is of a presettable type and is loaded with any preset value in accordance with a program from the instruction bus IB. To the frequency divider 113 is applied an output from a NAND gate 115through an inverter 114. The output 10 0 from the above described frequency divider 102 and the output from the NOR gate 116, that is, the output of the frequency divider 113 are applied to the NAND gate 115. A signal GTIMER START is applied to a reset input R of the frequency divider 113 through the NAND gates 117 and 118 and the signal GTIMER START is applied to one input of the NOR gate 116 through the NAND gate 119.Thus, the frequency divider 113 outputs a signal GTIMER OUT when a predetermined time period passes after a GTIMER START instruction is executed and the general timer 5 starts, the predetermined time period being set by the outputs IROUTO-IROUTS of the instruction bus IB. The signal GTIMER OUT can be used, for example, for determining whether a certain switch is kept depressed for more than one second.

The detail of the clock generator 2 is shown in Fig.

4. The clock generator 2 comprises a counter 121.

The counter 121 is structured by three stages of flip-flops, the outputs T1, T2, T2, T3 and T3 being withdrawn from these stages and being properly coupled to NOR gates 122-125. The frequency divided output ill from the reference signal generating circuit 1 (Fig. 3) is applied to the input terminal IN of the counter 121 through the NOR gate 126. On the other hand, the NOR gates 127 and 128 structure a flip-flop, the output of the NOR gate 127 being applied to the NOR gate 128 and the OR gate 129 the output of which is applied to a reset terminal R of the counter 121.To the NOR gate 128 is applied a stop signal CLK STOP outputted from the state control circuit 4 and to the NOR gate 127 are applied interrupt signals INTO, INT1, INT2 and INT3 through the NAND gate 130, an operation starting signal CLK START, a timer output GTIMER OUT and an initial signal MR which is outputted when a power supply is rendered on. The initial signal MR is also applied to an OR gate 129. The output from the NOR gate 126 is withdrawn as a reference clock CLK and a clock pulse signal CP is obtained from the output T1 of the counter 121. The respective system clocks T1 -T4 are outputted from the NOR gates 122-125. The NAND gate 131 receives three signals CLK, CP and T3 and thus a signal T3. CP. CLK is outputted from an inverter 132. Timing charts of outputs from the clock generator 2 as shown in Fig. 4 are shown in Fig. 5.

The detail of the switch input circuit 3 is shown in Fig. 6. It is pointed out in advance that circuits associated with terminals Ml -M4 (Fig. 1) are omitted in Fig. 6. External terminals S1-S4 are connected to input circuits 141-144 each of which has an identical circuit structure and the switches SW1-SW4 are connected to the external terminals S1-S4. Each of the input circuits 141-144 comprises a chattering preventing circuit 145, a NOR gate 146, latch circuits 147 and 148, an inverter 149 and NOR gates 150 and 151.The chattering preventing circuit 145 removes a chattering caused at the time of switching of the switches SW1-SW4 by means of a frequency divided output 810 which is applied from the reference signal generating circuit 1 through the NAND gates 152 and 153, the signal, the chattering of which is removed, being applied to the NOR gate 146 and also being applied to a NOR gate 146. An output Q of a D-type flip-flop to which an output of the NAND gate 154 is applied the NOR gate 146 so that the signals from each of the chattering preventing circuits 145 are delayed and outputted from the NOR gate 146. The outputs from the NOR gates 146 are connected to corresponding bits DB0, DB1, DB2 and DB3 in the data bus DB, respectively, through corresponding transmission gates 156, respectively.

The latch circuit 147 and the NOR gate 150 operate when the switches SW1-SW4 are closed and the latch circuit 148 and the NOR gate 151 operate when the switches SW1-SW4 are opened. These operations are determined by the switch operation designating signals S1 UP-S4 UP and S1 DOWN-S4 DOWN from the state control circuit 4, the designating signals being applied to the reset terminal R of the latch circuits 147 and 148. The frequency divided output 10 is applied to the latch circuits 147 and 148 through the NAND gates 152 and 153. Each output of the NOR gates 150 and 151 is applied to the NOR gate 157.The output from the NOR gate 157 is applied to the NAND gate 152 to control the frequency divided output 10 and also is applied to the clock generator 2 as an operation starting signal CLKSTARTthrough an inverter 158.

On the other hand, an interrupt generating circuit 159 comprises an R-S flip-flop 160 which is set if it is possible to output an interrupt signal when any of the switches SW1-SW4 is closed, and the set output controls a NAND gate 162 and a NOR gate 146 through an inverter 161. The circuit 159 further comprises a latch circuit 163 and a NOR gate 164 for extracting the edge of the signal outputted from the NAND gate 162, and a flip-flop 165 receiving at the set input thereof an output from the NOR gate 164.

The flip-flop 165 is set by the output from the NOR gate 164 to store that there is an interruption request and then outputs an interrupt signal INT3. Furthermore, a flip-flop 166 is provided for storing whether a state is that an interrupt signal can be outputted therefrom or whether the output of the switch data is inhibited.

Next, an operation of the circuit as shown in Fig. 6 will be described. If the output from the NOR gate 157 is "1", an operation starting signal CLK START is "0" and thus the clock generator 2 is not instructed to start its operation. If a switch data hold resetting signal S - RESET is "1", the frequency divided output 1 0 is outputted through the NAND gates 152 and 153 and thus a clock is supplied with the latch circuits 147, 148 and 163 and the clock terminal B of the D-type flip-flop 155. On the other hand, in case where the interrupt generating circuit 159 is not in the set state, the output "0" of the inverter 161 is applied to the NOR gate 146.Then, for example, if and when the switch SW1 is closed and the voltage VOID, that is, "1" is applied to the external terminal S1, the output of the chattering preventing circuit 145 changes from "1" to "0" and the output of the NAND gate 154 becomes "1". The D-type flip-flop 155 is inverted after a delay of one cycle with respect to the frequency divided outputs 10 and the output Q, "0", is applied to the NOR gate 146. The NOR gate 146 becomes conductive by the output 0 which is "0" and thus outputs a signal "1" indicating that the switch SW1 is closed. At that time, if and when a switch operation designating signal S1 UP which is applied to the reset terminals R of the latch circuit 147 is "1", that is, when the closure of the switch SW1 is not instructed, the latch circuit 147 remains in the reset state and the output of the NOR gate 150 is "0". Even if the switch operation designating signal S1 DOWN to the latch circuit 148 is "0", the output of the NOR gate 151 is "0" since the latch circuit 148 and the NOR gate 151 operate at the time of falling edge of an input signal. Thus, the output of the NOR gate 157 remains "1" and an operation starting signal CLK START is not outputted.On the other hand, if a switch operation designating signal S1 UP is "0", the output Q of the latch circuit 147 to which an inverted signal of the output of the NOR gate 147 is applied through the inverter 149 is "0" and thus the output "1" is outputted from the NOR gate 150.

Therefore, the output of the NOR gate 157 becomes "0", and the operation starting signal CLK START which is "1" is outputted and then an operation is restarted if the operation of the clock generator 2 is stopped. In addition, since the output "0" of the NOR gate 157 disables the NAND gate 152 to pass the frequency divided output 1 0, the operations of the chattering preventing circuit 145, the D-type flip-flop 155 and the latch circuits 147 and 148 are stopped and thus a switch data is held. In response to the start of the operation of the clock generator 2, the program in the read only memory 7 shown in Fig. 2 proceeds and if an instruction in the program indicating the input of the switch data is executed, the transmission gates 156 are opened and the switch data is sent to the data bus DB.

If and when a signal S- RESET resetting the hold of the switch data becomes "0", the output of the NAND gate 153 becomes "1". By this signal, the latch circuit 147 is inverted and thus the output of the NOR gate 150 becomes "0" so as to make the output of Q be "1". As a result, the output of the NOR gate 157 becomes "1" and the operation starting signal CLK START becomes "0", and thus the NAND gate 152 passes the frequency divided output 810.

In case where the switch SW1 is opened, the output of the chattering preventing circuit 145 changes from "0" to "1" and the output of the NOR gate 146 changes from "1" to "0". As described in the foregoing, if a switch operation designating signal S1 DOWN, "0", is applied to the latch circuit 148, the output of the NOR gate 151 becomes "1" and the operation starting signal CLK START, "1", is outputted and thus the switch data is held.

Thus, it is one of the features of the present embodiment that it is possible to setthe designation of the switch operation by selecting the switch designating signals Si UP-S4 UP and S1 DOWN-S4 DOWN applied to the reset terminals R of the latch circuits 147 and 148 and it is possible to start an operation of the clock generator 2 when the designated switch is operated. As the switch designating signals S1 UP-S4 UP and S1 DOWN-S4 DOWN, the outputs of the flip-flops or latch circuits provided in the state control circuit 4 shown in Fig. 7A in detail are used, the number of the flip-flops or latch circuits corresponding to the number of the switch designating signals. The flip-flops are set by the switch operation designating instruction.For example, assuming that the instruction code is 110000XXXXXXXX, the flip-flops are set by the data IROUT0-IROUT7 in the 8 least significant bits.

On the other hand, it is possible to process an interrupt by means of closure of any one of switches SW1-SW4. More particularly, if and when an instruction for making an interrupt be processed by a switch is executed, a pulse of "0" occurs in an interrupt set signal SWLOCK from the state control circuit 4. The flip-flop 166 is set by the SWLOCK and thus the output Q thereof becomes "0" and the output of the NOR gate 167 becomes "1". The flip-flop 166 to which the "1" from the NOR gate 167 is applied is set and thus the output of the inverter 161 becomes "1". Accordingly, the NAND gate 162 becomes conductive and the NOR gate 146 is disabled. If, in such a state, any of the switches SW1-SW4 is closed, the output of the NAND gate 154 becomes "1", but the output of the chattering preventing circuit 145 is not outputted from the NOR gate 146.When the output of the NAND gate 154 becomes "1", the output of the NAND gate 162 becomes "0" and thus the latch circuit 163 and the NOR gate 164 apply a pulse of "1" to the flip-flop 165 at the time of the falling edge of the output of the NAND gate 162. The flip-flop 165 is set by the pulse so that an output, that is, an interrupt signal INT3 becomes "0". The interrupt signal INT3 "0" restarts the operation of the clock generator 2 and a predetermined interrupt processing is made. When an interrupt is accepted, the pulse of a reset signal INT3 RESET becoming "1" occurs from Fig. 9 (described subsequently) so that the latch circuit 163 and the flip-flops 165 and 166 are reset.On the other hand, the flip-flop 160 is reset when the switches SW1-SW4 are opened and the output of the NOR gate 168 to which the outputs of the D-type flip-flop 155 and the NAND gate 154 are applied becomes "1".

An interrupt generating circuit 159 can forcibly provide an interrupt by an instruction. If and when an instruction of interruption request is executed, an interruption request signal INT3 REQ "0" is outputted from the state control circuit 4 (Fig. 7A), and correspondingly, the flip-flop 165 is set through the inverter so that an interrupt signal I NT3 "0" is outputted. On the other hand, if and when an interrupt generating circuit 159 is in a set state, then the flip-flops 166 and 160 are reset. The interruption request instruction is executed when, for example, a forcible interrupt is entered and generation of an alarm sound is stopped in case where operation of a mode change and the like are made during alarming.

Meanwhile, the signals S1 OUT and S2 OUT from the circuit 3 are applied to the chronograph circuit 6, respectively.

Figs. 7A and 7B show in detail a portion of the state control circuit. The state control circuit 4 is responsive to instruction outputs lROUTfromthe instruction bus IB for outputting a control signal corresponding to the instruction. The switch designatingflip-flop circuit 170 comprises eight D-type flip-flops or latch circuits and the outputs IROUTO, lROUT1, lROUT2, lROUT3, IROUT4, IROUTS, TROUT6 and IROUT7 from the instruction bus IB are applied to corresponding flip-flops 178, 177, 176, 175, 174, 173, 172 and 171, respectively. The outputs from the instruction decoder 179 are applied to the clock inputs per of these flip-flops 171-178. From the flip flops 171, 172 178, signals > , S1 DOWN, . .., S4 DOWN are outputted for controlling the states of the switches. These signals are applied to the switch input circuit 3 (Fig. 6), as described in the foregoing. The instruction decoder 179 receives the inputs IROUT8-lROUT13 and a signal T3 CP CLK to output a signal S - RESET through an inverter. A general timer control gate circuit 180 comprises two NAND gates, these NAND gates receiving outputs IROUT7 and IROUT8 from the instruction bus IB, respectively. Two gates included in the gate circuit 180 are controlled by the output from the instruction decoder 181. The instruction decoder 181 receives the outputs IROUT9-IROUT13 from the instruction bus IB and the signal T3 cup CP.CLK.The timer control gate circuit 180 outputs signals GTIMER START and GTIMER RESET to the general timer 5 shown in Fig.

3.

Referring to Fig. 7B, the instruction decoder 182 receives the outputs IROUT8-lROUT13 from the instruction bus IB and the signal T3 CP- CLK to provide the output to the NAND gates 183 and 184.

The outputs TROUT3 and IROUT1 from the instruction bus IB are applied to the other inputs of the NAND gates 183 and 184, respectively. Accordingly, the NAND gate 183 outputs a signal INT3 REQ in response to the instruction output IROUT3, and the NAND gate 184 outputs a signal CHR RESET through an inverter in response to the instruction output IROUT1. The instruction decoder 185 receives the outputs IROUT7-lROUT13 from the instruction bus IB and the signal T3 CP CLK to output a signal RTS.

The instruction decoder 186 receives the outputs IROUT8-lROUT13 from the instruction bus IB and the signal T3 CP CLK to output a signal CLK STOP. The instruction decoder 187 receives the outputs IROUT9-IROUT13 from the instruction bus IB and the signal T3 CPw CLK to provide the outputs to the respective one inputofthe NAND gates 188,189 and 190. The output IROUTS from the instruction bus IB is applied to the other input of the NAND gate 188, the output from the NAND gate 188 being a signal SWLOCK. The instruction decoder 191 receives the outputs IROUT9-IROUT13 from the instruction bus IB and the signal T3. CP- CLK to provide the outputs to the NAND gates 192, 193 and 194.The output IROUT1 from the instruction bus IB is applied to the other input of the NAND gate 192, the output of the NAND gate 192 becoming a signal LAP RESET through an inverter. The output IROUT2 from the instruction bus IB is applied to the respective other inputs of the above described NAND gates 189 and 193, the outputs from the respective NAND gates 189 and 193 being applied to the flip-flop 195. The output of the flip-flop 195 becomes a signal "CDB to DEC". The output IROUTO from the instruction bus IB is applied to the respective other inputs of the NAND gates 190 and 194, the outputs of the respective NAND gates 190 and 194 being applied to an input of the flip-flop 196. The output of the flip-flop 196 becomes a signal CHRONO.

The signals S1 UP, S1 DOWN,. . ., S4 DOWN, S - RESET, INT3 REQ and SWLOCK are applied to the switch input circuit as shown in Fig. 6, respectively.

The signals GTIMER START and GTIMER RESET are applied to a general timer 5 shown in Fig. 3. The signal CLK STOP is applied to the clock generator 2 as shown in Fig. 4. The signals CHR RESET, CDB to DEC, CHRONO and LAP RESET are applied to the chronograph circuit 6 shown in Fig. 8, respectively. A signal RTS which is a return instruction to a main routine is applied to the interrupt control circuit 18 as shown in Fig. 9.

Fig. 8 is a circuit diagram showing a chronograph counter 6 and the peripheral portion thereof as shown in Fig. 2. A counter 201 is a 10-nary counter, the content of the counting being applied to a transmission gate 202 through a chronograph data bus CDB of 4 bits. The data bus DB is connected to a transmission gate 203. These transmission gates 202 and 203 are controlled by a data bus switching signal DBCHANGE outputted from the NOR gate 204, so that either of the data bus DB and the chronograph data bus CDB is connected to the decoder 15 in a switching manner. A 1/100 sec signal made by a reference signal generating circuit 1 is applied to an input of the counter 201 through a NAND gate 206 controlled by an output 0 of a T-type flip-flop.An output S1 OUT from the switch input circuit 3 is applied to the T-type flip-flop 205 through a NAND gate 207 controlled by a chronograph mode signal CHRONO outputted from the state control circuit 4.

The output S1 OUT is outputted when the switch SW1 connected to the external terminal S1 is closed, as described in the foregoing. Accordingly, in case of a chronograph mode, the closure of the switch SW1 inverts the T-type flip-flop 205, so that a 1/100 sec signal is or is not applied to the counter 201. More particularly, it can be said that the circuit 208 controls the start and the stop of the chronograph.

On the other hand, the output from the counter 201 is a 1/10 sec signal which is applied to the latch circuit 209 and the NOR gate 210. The latch circuit 209 and the NOR gate 210 outputs a pulse of "1" when the 1/10 sec signal is inverted from "1" to "0", and the pulse of "1" sets a flip-flop 211 for an interruption and thus an interrupt signal INT1 is outputted. The latch circuit 209 and the flip-flop 210 are reset by a signal INT1 RESET outputted from an interrupt control circuit 18 (which is included in a control circuit 11 in Fig. 2. see Fig. 9) when an interrupt INT1 is accepted. Accordingly, the interrupt signal lNT1 is outputted every 1/10 seconds.

A T-type flip-flop 212 is a flip-flop for controlling a lap, to which an output S2 OUT from the switch input circuit 3 is applied through the NAND gate 213 controlled by a chronograph mode signal CHRONO.

Accordingly, the flip-flop 212 is inverted by closure of the switch SW2 connected to an external terminal S2 of the switch input circuit 3, so that a lap signal LAP is outputted. The lap signal LAP is applied to an input of a D-type flip4lop 214 and the output ofthe NOR gate 214 is applied to the clock terminal per thereof through an inverter. The D-type flip-flop 214 is adapted to store whether the lap is made before or after an interrupt signal INT1 is outputted, the output therefrom being outputted as a lap processing signal LAPSAMPL.In addition, the lap signal LAP is used as a signal for controlling rewriting operation of the latch circuit 16 shown in Fig. so that, if and when the lap signal LAP is "1", the rewriting operation of segment signals a-g outputted by converting the count data of the counter 201 by the decoder 15 is stopped and thus the segment signals a-g previously stored are held and outputted to a displaying apparatus. More particularly, while the signal LAP is "1", the lap data of the digit of 1/100 second is displayed.On the other hand, the data of the digit or unit larger than the unit of 1/10 second is processed in an interrupt processing T7, wherein a lap is obtained by not executing a display program when the lap processing signal LAPSAMPL is "1" and by displaying the data that a carry processing is made when the lap processing signal is "0".

In a chronograph mode, in order to display the 1/100 second digit, the count data of the counter 201 is always applied to the decoder 15, so that the display must be made to follow the data varying every 1/100 second. On the other hand, concerning the data of the digit larger than the 1/10 second digit, the data stored in the random access memory 14 is sent out to the data bus DB and must be applied to the decoder 15. Switching signals CDB to DEC outputted from the state control circuit 4 are applied through the inverter 215 to the NOR gate 204 outputting a data bus switching signal DBCHANGE.

The switching signal CDB to DEC become "1" when an instruction for making the chronograph data bus CDB be applied to the decoder 15 is executed, and become "0" when an instruction for making the data bus DB be applied to the decoder 15 is executed.

Furthermore, the output of the NOR gate 216 is applied to the NOR gate 204 and the NOR gate 216 and the NAND gate 217 apply the "1" to the NOR gate 204, when the instruction is a display instruction, in response to the outputs IROUT12 and IROUT13 and the output DBUSENA in the control circuit 11 indicating a data transfer timing of the data bus DB. In the present embodiment, the display instruction is of 14 bits instruction code, and, of these, the thirteenth bit is "1" and the twelfth bit is "0". Accordingly, in the chronograph mode, if and when the instruction for making the chronograph data bus CDB be applied to the decoder 15 is executed, the output of the inverter 215 becomes "0" and the output of the NOR gate 216 is also "0", and thus the data bus switching signal DBCHANGE becomes "1" and the chronograph data bus CDB is connected to the decoder 15.If and when, in order to display the data of the digit larger than the 1/10 second digit, the display instruction is executed with the state being maintained, the output of the NOR gate 216 becomes "1 " and thus the data bus switching signal DBCHANGE becomes "0" and the data bus DB is connected to the decoder 15. Since the output of the NOR gate 216 again becomes "0" after execution of the display instruction, the chronograph data bus CDB is connected to the decoder 15. In such a way, the count data of the counter 201 is always displayed except for the display of the digit larger than the 1/10 second digit.

The above described signal DBUSENA which is applied to one input of the NAND gate 217 is an output of a flip-flop structured by NOR gates 218 and 219. A clock T1 from the clock generator 2 is applied to the set input of the flip-flop and a clock T2 and a clock pulse signal CP are applied to the reset input thereof th rough the NAND gate 220 and an inverter.

The control circuit 11 in Fig. 8 comprises a NOR gate 221 receiving the above described signal DBUSENA and the outputs lROUT9-lROUT13 from the instruction bus IB and two transfer gates 222 and 223 are controlled by the output of the NOR gate 221.

The transfer gate 222 applies the output of the flip-flop 214, that is, a signal LAPSAMPL to the data bus DB and the transfer gate 223 applies the output of the flip-flop 205, that is, a signal START to the data bus DB.

Fig. 9 is a block diagram showing an interrupt control circuit 18 included in the control circuit 11 (Fig. 2). The interrupt control circuit 18 receives the above described four interrupt signals, that is, INTO, INT1, rim2 and INT3. The interrupt signal INTO is outputted from the general timer 5 shown in Fig. 3 every predetermined cycle, for example, 62.5 m sec.

For example, the change of the state of the external terminals M1-M4 and S1-S4 of the switch input circuit 3 is detected every predetermined cycle. The signal INT1 is outputted from the flip-flop 211 in the chronograph circuit 6 shown in Fig. 8, and in response to this signal, the process of the chronograph mode is made. The signal INT2 is outputted from the reference signal generating circuit 1 shown in Fig. 3 every 0.5 seconds, and in response to this signal, counting processing of a current time is made. The signal INT3 is outputted from the interrupt generating circuit 159 included in the switch input circuit 3 shown in Fig. 6 and, in response to this signal, the processing for stopping generation of alarm sound is performed.These interrupt signals INTO, INTO, INT2 and INT3 are applied to the terminals D of the corresponding D-type flip-flops 231,232,233 and 234 and the clock T4 from the clock generator 2 is applied to the clock terminal of the flip-flops 231-234. Accordingly, the interrupt control circuit 18 detects the presence or absence of an interrupt signal every clock T4. The outputs Q of the flip-flops 231-234 are applied to an interrupt control 235 and an interrupt address generating circuit 236.

The interrupt address generating circuit 236 provides "1" or "0" to two predetermined bits of a program counter (described subsequently) so as to assign an absolute address for interrupt processing.

More particularly, if and when an interrupt is caused, the program counter 8 comprises 11 bits of 000000iXX00, wherein 0,0 are applied to the X, X in INTO, 0, 1 is applied to the X, X in Into, 1,0 is applied to the X, X in INT2, and 1,1 is applied to the X, X in INT3. The output of a decoder (not shown) included in the interrupt address generating circuit 236 is applied to an interrupt reset circuit 237. The decoder included in the interrupt address generating circuit 236 decodes what the interrupt caused at that time is, and generates the above described interrupt address and applies the signal to the interrupt reset circuit 237.

The interrupt control circuit 18 comprises a function for determining prior of interrupt just as a general microcomputer and in this embodiment, the priority in order of INTO, INT1, INT2 and INT3 is determined. The interrupt reset circuit 237 receives a signal INTfrom the interrupt control 235 and the signal T3 CP CLK from the clock generator 2, and at the timing of the signal T3 CP Hz CALK, signals INTO RESET, INT1 RESET, INT2 RESET and INT3 RESET for resetting the flip-flop causing an interrupt source are applied to corresponding circuits 5 (Fig. 3), 6 (Fig.

8),1 (Fig.3) and 159 (Fig. 6), respectively, in accordance with the priority. Then, at the next T4 timing, a signal from a flip-flop reset is stored in a corresponding one of the flip-flops 231-234. In case where, in the interrupt control 235, an interrupt having a higher priority is caused when a certain interrupt processing is executed, the processing being executed is stopped and a new interrupt is preferentially executed. To this end, a stack 9 (Fig. 2) is employed. The interrupt control 235 further receives a signal RTS (Fig. 7B) from a control circuit. If all of the interrupt processings are already terminated when the signal RTS which is a return instruction is applied, an interrupt enable signal is outputted.To the contrary, if it is in an interrupt pending state when the signal RTS is provided, the pending interrupt processing is executed.

Fig. 10 is a block diagram showing portions associated with control of a program address. A program counter 8 comprises a predetermined number of bits (11 bits in this embodiment) of the D-type flip-flops 80,81 . . 90. The respective outputs Q of the flip-flops 80-90 are applied to the read only memory 7 as addresses thereof. Accordingly, the read only memory 7 reads out an instruction of 14 bits from an address assigned by "1 " or "0" of the output 0 of each of flip-flops 80-90 in the program counter 8, the instruction read out being applied to the instruction register 10 (Fig. 2). A clock T1 from the clock generator 2 (Fig. 4) is applied to the clock terminals per of the flip-flops 80-90. An incrementer 19 is connected to the program counter 8.The incrementer 19 increments the content in the program counter 8 and, in this embodiment, is characterized in that whether incrementation is made or not is controlled by a NAND gate 241. More particularly, when the output of the NAND gate 241 is "1 ", the content of the program counter 8 is incremented by (+1), and when the output is "0", the content is not incremented. To one input to the NAND gate 241 is applied an output BSR + INT from the OR gate 244 to which a signal lNTfrom an instruction control circuit 18 (Fig. 9) and a signal BSR from an instruction decoder included in the control circuit 11 are applied, and to the other input is applied a signal SCP from an instruction decoder included in the control circuit 11.The instruction decoder receives the outputs IROUT8-lROUT13 of the instruction bus IB, while the signal SCP is an instruction for stopping an operation of the clock generator 2 (Fig. 4). The signal BSR is a signal which is outputted from the control circuit 11 when a jump instruction is executed in a normal operative state. The incrementer 19 comprises exclusive OR gates 190, 191 200, to the respective one inputs of which are applied corresponding outputs Q of the flip-flops 80-90 included in the program counter 8. To the respective other inputs of the exclusive OR gates 191-200 are applied corresponding outputs from AND gates 251-260.To the respective one inputs of the AND gates 251-260 is applied an output from the NAND gate 241 and to the other inputs are applied corresponding outputs from the flip-flops 80-89 in lesser significant bits included in the program counter 8. Accordingly, when the output from the NAND gate 241 is "1 ", the output incremented by + 1 from the flip-flops 80-89 in the program counter 8 is withdrawn from AND gates 251-260, that is, the exclusive OR gates 191-200 and when the output from the NAND gate 241 is "0", the content in the program counter 8 at that time is outputted from the exclusive OR gates 190-200. An AND gate is not connected to the exclusive OR gate 190 in the least significant bit.

The outputs in the respective bits from the exclusive OR gates 190-200 in the incrementer 19 are applied to corresponding input terminals IN0-IN10 in the stack 9. The stack 9 is a push-down stack, wherein a read operation, that is, a pop-up operation is performed when a signal applied to the terminal RNV is "1" and a write operation, that is a push-down operation is performed when the signal is "0". An output from the NAND gate 242 is connected to the terminal RNV and to the output to the NAND gate 242 are applied a clockT4, a clock pulse signal CP and the output BSR + INT from the OR gate 244.

Accordingly, the stack 9 performs a read operation when both of an interrupt signal INT and a signal BSR are not applied, and performs a write operation when one of the signal INT and the signal BSR is applied. The stack 9 comprises output terminals OUTO-OUT10. An instruction address control circuit 20 is provided between the stack 9 and the program counter 8. The instruction address control circuit 20 comprises gate circuits 270-280 corresponding to 11 bits, respectively, and each of the gate circuits 270-280 comprises three AND gates G1 -G3 and one OR gate G4 in an identical manner. On input of each of AND gates G1 in the gate circuits 270-280 is applied to a corresponding output from the exclusive OR gates 190-200 included in the incrementer 19 and to the other input is applied an output from a NOR gate 243.To the input to the NOR gate 243 are applied an output BSR + INTfrom the OR gate 244 and a signal RTS (Fig. 7B) from the instruction decoder included in a control circuit. In addition, the signal RTS is applied to one input of the respective AND gates G2 in the gate circuits 260-270 and corresponding one of the outputs OUT0-OUT10 from the stack 9 is applied to the other inputs to the gates G2. A signal INT is applied to one input of each of the AND gates G3 in the gate circuits 260-270 and a corresponding bit output from the interrupt address setting circuit 21 is applied to the other inputs. To the interrupt address setting circuit 21 are applied an address signal INTADDRESS 1 and INTADDRESS 2 from an interrupt address generating circuit 236 included in an interrupt control circuit 18 (Fig. 9).

Accordingly, if and when an interrupt is caused and a signal INT is outputted, the program counter 8 is adapted such that the flip-flops 80-90 in the program counter 8 are set based on the program address 0000001XX00 from the interrupt address setting circuit 21 through the respective AND gates G3, as described in the foregoing.

Fig. 11 is a timing diagram explaining an operation of Fig. 10. In a normal operation, that is, when the clock generator operates, the output from the NAND gate 241 becomes "1" and the incrementer 19 is enabled when an interrupt signal INT and a signal BSR both are "0". Accordingly, a program address stored in the program counter 8 is incremented by + 1 by the incrementer 19 to be applied to the respective AND gates G1 in the address control circuit 20 through the respective exclusive OR gates 190-200. At that time, since the output from the NOR gate 243 also becomes "1", the incremented program address from the incrementer 19 is provided, at the timing of the clock Tri, to the flip-flops 80-90 in the program counter 8 through the corresponding AND gates G1.If and when a jump instruction is executed with the above described state, a signal BSR becomes "1" and the AND gate G1 is closed.

Accordingly, the program address stored in the program counter 8 is incremented by +1 by the incrementer 19 and the incremented program address is stored in the stack 9 at the timing of T4 CP.

Furthermore, in case where an interrupt signal INT becomes "1" when the clock generator 2 operates, the output from the NAND gate 241 becomes "1" and hence the program address stored in the program counter8 is incremented by +1 by the incrementer 19 and the incremented program address is stored in the stack 9 at the timing of T4 CP. On the other hand, the "1" of the signal INT causes the respective NAND gates G3 to become conductive and hence the outputs from the interrupt address setting circuit 21 set each of flip-flops 80-90 in the program counter 8 through the respective AND gates G3, at the timing of the clock.

If an interruption is caused when the operation of the clock generator 2 is stopped by an instruction SCP from the control circuit 11, the incrementer 19 is disabled by the output "0" from the NAND gate 241.

Accordingly, the respective outputs from the flipflops 80-90 in the program counter 8 are applied to the corresponding inputterminals IN0-IN10 in the stack 9 through the exclusive OR gates 190-200.

Then, the terminal RNV of the stack 9 becomes "0" at the timing determined by T4 CP and hence the program address in the program counter 8 is written into the stack 9 at that timing. At that time, since the respective AND gates G3 included in the address control circuit 20 are opened, at the timing of a next clock T1, an interrupt address from the interrupt address setting circuit 21 are set in the flip-flops 80-90 in the program counter 8 through the respective AND gates G3.

If and when a return instruction signal RTS is outputted from the instruction decoder (Fig. 7B) included in the control circuit, the respective AND gates G2 included in the address control circuit 20 are opened and the content of the output terminals OUT0-OUTi0 in the stack 9 are set in the correspond ing flip-flops 80-90 in the program counter 8 at the timing of the clock T1. Accordingly, if the clock generator 2 is stopped by the signal SCP when the interrupt is caused, the program address at the time when the interrupt was caused is again set in the program counter 8 in response to the return instruction signal RTS outputted after the interrupt processing.To the contrary, if an interrupt is caused when the clock generator 2 is operating, the program address from the stack 9 previously incremented by +1 by the incrementer 19 is set in the program counter 8 in response to the return instruction signal RTS outputted at the time of termination of the interrupt. Thus, corresponding to the state of the clock at the time when the interrupt is caused, the program address to be set in the program counter 8 is changed in response to the return instruction signal RTS.

Fig. 12 is a diagram showing one example of a storage format for a random access memory. In this embodiment, the random access memory comprises storage areas from "00" to "3F", the storage areas from "00" to "06" being used for chronograph mode. The storage areas from "10" to "1A" are utilized as flag areas and the storage areas from "28" to "2B" and from "31" to "37" are used for counting a current time. There are LAP, SNOOZE REQ, MODE CHANGE, CHRONO RESET, CHRONO STOP and 1/2 sec FLAG in the flag areas. Flags indicating the respective modes are formed in the area of "17".

It should be noted that Fig. 12 merely shows in detail one example of the storage format to the extent that it is necessary for explaining the present invention in the following.

Fig. 13 and Figs. 14 to 18 are flow charts showing example of programs written in the read only memory 7, wherein Fig. 13 shows a main program, Figs. 14to 17 show a program for interrupt processing, and Fig. 18 shows a program for a chronograph mode. The operation will be described using Fig. 13 and Figs. 14 to 18.

First, if and when a power supply is applied, an initial clear is enabled and each circuit is reset. Thus, the program counter 8 assigns 0 address of the read only memory 7. A program for initialization is written from the 0 address and "0" or a predetermined data is stored in the random access memory 14 and initialized through an execution of the program.

Then a program for mode change is executed. The program makes the data indicating the switching of the switch be inputted from the switch input circuit 3 into the processor CPU through a data bus DB and determines based on a content of the data which of a current time mode, an alarm mode, a timer mode or a chronograph mode and in addition, the other mode if a further function is provided, is selected. In the mode change program, it is determined whether the mode is a correction mode in each mode and a flag within an area "17" (Fig. 12) ofthe random access memory 14 corresponding to each mode is set. Then, a predetermined address for the read only memory 7 in which the selected program is written is assigned and the program jumps thereto. In the present embodiment, a mode selection is made by switches (these switches are designated as MS1-MS4 and SW4) connected to the external terminals M1-M4 and S4. However, the switches MS1-MS4 are not shown. A programming is made so that executions of the correction, lighting a lamp and the stop of alarm sound are performed by the switches (these switches are designated as SW1-SW3) connected to the external terminals S1-S3. However, it can be readily achieved by a program change that a mode selection or other operations is performed by using 2 to 4 switches.

In case of a current time mode, first, a current time is displayed. More particularly, at this step, according to a display instruction which is capable of addressing the random access memory 14, the data of second, minute, hour, month, date, a day of the week and the like stored in predetermined address (in Fig. 12, corresponding to the areas "28" to "2B" and "31" to "37") in the random access memory 14 for each digit is sequentially addressed and the data is sent out to the data bus DB and is stored in the latch circuit 16 corresponding to an element to display a segment signal converted in the decoder 15. At that time, by executing in advance the instruction for connecting the data bus DB to the decoder 15, it is possible to separate the chronograph data bus CDB in case where the mode is changed from the chronograph mode.In case of "hour" display, it is determined which of 12 hours system and 24 hours system display is selected and the time data in the random access memory 14 is processed by a program corresponding to the display. In case of "a day of the week" display, the function of the decoder 15 is switched by an instruction so that the function for "a day of the week" conversion is selected, and thereafter a day of the week data is applied, whereby any of the flag segments FS1-FS7 in Fig. 1 is driven.

Meanwhile, a display is made even if an operation of the clock generator 2 is stopped, since the latch circuit 16 continues to output the segment signals stored until the segment data is rewritten.

In the following, a switch is set. At this step, the flag indicating a correction mode provided in the random access memory 14 is determined, and the closure of the switch SW1 if in a normal mode or the closure of the switches SW1-SW3 if in a correction mode is designated. More particularly, the execution of the instruction causes the state control circuit 4 to control the switch input circuit 3 by a switch control signal SWCON and makes an operation starting signal CLK START be outputted only if the designated switch is operated, that is, closure of the switch SW1 or closure of any of the switches SW1-SW3 is made.

Upon completion of switch designation, an instruction "SCP" for stopping an operation of the clock generator 2 is executed. The instruction causes the state control circuit 4 to output a stop signal CLK STOP (Fig. 7B) to stop an operation of the clock generator 2 so that an operation of a program is stopped. Accordingly, a consumed electric current is largely reduced during the stop period.

The time when the operation as is restarted is that the time when the switch operation as designated above is performed, an interruption request INTO, INT1, INT2 or INT3 is provided and the general timer 5 counts up. In case of the interruption request INTO, INT1, INT2 or INT3, an operation of the central processing unit is again stopped after processing of an interrupt since an address indicating a stop instruction (SCP) is stored in the stack 9. More particularly, in case of an interrupt, although an operation of the clock generator 2 is initiated, the content of the program counter 8, that is, the content for addressing the stop instruction (SCP) stands by in the stack 9 and an address indicating an interrupt processing program as shown in Figs. 14 to 17 is set in the program counter 8.Then, upon completion of the interrupt processing, the address which stands by in the stack 9 is set in the program counter 8 and hence the stop instruction (SCP) is again executed and the operation is stopped. On the other hand, an operation starting signal CLK START outputted when the designated switch operation is performed, or the timer output GTIMER OUT from the general timer 5 causes the clock generator 2 to restart and thus the program proceeds.

The next program investigates MODE CHANGE flag (Fig. 12) in the random access memory 14 and determines whether there is a mode change request.

If there is a mode change request, the program jumps to the above described mode change program and if there is no mode change request, the program proceeds to a next program. The set or reset of the MODE CHANGE flag is made by an interrupt processing INTO. In the interrupt processing by INTO, as described subsequently, the states of the switches MS1 -MS4 and SW4 for selecting a mode are periodically investigated and if it is a mode change, the flag is set to "1" and then the general timer 5 is made to start. Thus, in a mode change request, the clock generator 2 is operated using the timer outputs GTIMER OUT so that the mode change is made.

On the other hand, in case of no mode change request, which corresponds to the case where the switch is operated, the next program determines whether it is a correction mode or not and which of the switches SW1-SW3 is closed so that the processing corresponding to the operation is made. For example, in case where the switch SW1 is closed in a normal mode, an instruction for lighting a lamp is executed, the external terminal LAMP in the state control circuit 1 is made to be "1", and the next instruction designates an opening of the switch SW1 and thus the stop instruction "SCP" for clock is executed. Then, once the switch SW1 is opened, the above described operation is again started, an instruction for turning out the lamp is executed and the program jumps again to a program for setting a switch.In case where the switch SW1 is closed in a correction mode, the data of the second stored in the areas "29" and "28" (Fig. 12) in the random access memory 14 is rewritten to "0". At that time, it is determined whether it is 29 seconds or 30 seconds and if it is over 30 seconds, carry processing is made.

In case where the switch SW2 or the switch SW3 is closed, the data of the hour or the minute stored in the areas "37", "36" or "35", "34" (Fig. 12) inthe random access memory 14 is transferred to the arithmetic and logical unit 12 wherein 1 is added, and then the result is written in the random access memory 14. Furthermore, in case where the switch SW2 or SW3 continues to be closed, a fast correction is made. In such a case, the correction is made using the designation of the switch operation and the stop instruction "SCP" for operation of the clock. More particularly, the general timer 5 is started by setting one second and then the stop instruction "SCP" is executed after designating the opening of the switches SW2 and SW3.Therefore, the time when the clock generator 2 starts to operate is that the time when the switch SW2 or SW3 is opened and the general timer 5 counts one second, and thus it is possible to determine whether the switch SW2 or SW3 is closed for a predetermined time period by determining the states of the switch SW2 or SW3. If the switch SW2 or SW3 is closed, 250 ms is set in the general timer 5 after 1 is added to the data of "hour" or"minute" in the random access memory 14 and then a program again jumps to a program designating the opening of the switches SW2 and SW3. As a result, the above described addition is repeated and fast forwarded until the switch SW2 or SW3 is opened.In this correction program, if and when the reset of second, and addition processing of minute or hour are performed, the data corrected by the display instruction is immediately sent out to the data bus DB and displayed. If and when the switches SW2 and SW3 are opened, a program jumps from the program for correction to the above described program for switch setting.

The alarm mode, timer mode and chronograph mode are also programmed in the same pattern as the above described present time mode.

In the alarm mode, the address in which an alarm time is stored in the random access memory 14 is designated and displayed in a digit sequential manner. The designation of switch selects closure of the switches SW1 -SW3 in the alarm setting mode and closure of the switch SW1 in the alarm display mode and thus an operation stop instruction "SCP" is executed as an instruction associated with designation of the switch. If and when there is no mode change request and the designated switch is closed, a program proceeds to a program for timer time set, display and lamp flashing.The alarm mode, if and when the switch SW1 is closed, the lamp lighting instruction, the designation for opening the switch SW1 and the operation stop instruction "SCP" are executed even if the mode is an alarm setting mode, and thus the lamp is lighted and turned out by executing the instruction for turning out the lamp after starting of the operation. On the other hand, in case where the switch SW2 or SW3 is closed, which means an alarm time setting mode, the minute or the hour in the alarm time is set. The same program as the correction program for a current time is used as this program, and the program for performing an addition process is used as a subroutine and a program is set so that the address in the random access memory 14 in which the hour or the minute of the alarm time is stored may be addressed.Of course, the content set are immediately displayed by the display instruction.

Similarly in the timer mode, a program for displaying a timer time period, a program for setting a switch and an operation stop instruction "SCP" are sequentially executed. The timer in this case is not a general timer 5, but a timer for second, minute and hour stored in a predetermined address in the random access memory 14. Accordingly, the display instruction address is the predetermined address in the random access memory 14. In the timer mode, there is no correction mode and when the switch is set, it is determined whether the alarm sound is caused or not. If the alarm sound is caused, the switches SW1 - SW3 are set to be closed, and if the alarm sound is not caused, only the switch SW1 is set to be closed. If and when the operation is restarted and there is no mode change, the program proceeds to the program for set of timer time period, display, start, stop and lamp flashing.If the mode is a mode in which an alarm sound is not caused when the switch SW1 is closed, the lighting and turning out of the lamp are performed by a lamp flashing program in the same manner as the current time mode and an alarm mode. On the other hand, if and when the switch SW2 or SW3 is closed in a mode in which an alarm sound is caused, the minute or the hour is corrected by a correction program. If and when the switch SW1 is closed in a mode in which an alarm sound is caused, the flag for timer start is set in the random access memory 14 in case where the time is set and no action is made in case where the timer is not set and thus a program proceeds to a program for setting a switch.

Now, a chronograph mode is briefly described, although the detail thereof will be described subsequently. In case ofthe chronograph mode, 1110 second, second, minute, hour of a chronograph time in the areas "00" to "06" (Fig. 12) in the random access memory 14 are sequentially displayed by a display instruction, and in addition, the data of the digit of the 1/100 second of the chronograph counter 201 is displayed by selecting the chronograph data bus CDB to the decoder 15 by the data bus DB and chronograph data bus CDB switching instruction.In such a way, the reason why the data of the1/100 second is directly applied to the decoder 15 is that if the display is made digit by digit by a program, a processing time is too long so that the data of the 1/100 second can not be followed and thus a precise display cannot be achieved.

In the switch setting, the switches SW1 and SW2 are set to be closed. Although, when the switch SW1 or SW2 is closed, the operation starts and the program proceeds, in the chronograph mode, the chronograph control signal CHRCON is outputted from the switch input circuit 3 independently of a program to control the chronograph circuit 6. More particularly, the chronograph control signal CHRCON outputted when the switch SW1 is closed sets or resets the flip-flop 205 for controlling the start and stop for the chronograph circuit 6 and the chronograph control signal CHRCON outputted when the switch SW2 is closed sets or resets the flip-flop 212 in Fig. 8.

On the other hand, a program determines whether the chronograph counter 201 starts or not, or is in a lap state or not by seeing a control flip-flop 205 in the chronograph circuit 6 and the flip-flop 212 for lap flag, and thus CHRONO STOP flag and LAP flag in the random access memory 14 are set or reset. In addition, if and when the switch SW2 is closed in the stop state, the chronograph data in the random access memory 14 is reset. At the end of the program, the chronograph data in the random access memory 14 is displayed by a display instruction and a program jumps to a switch setting. An addition processing for the chronograph data in the random access memory 14 is made by an interrupt signal INT1 outputted every 1/10 second from the chronograph circuit 6.

The interrupt processing INTO shown in Fig. 14 is achieved for each predetermined time period, for example, every 62.5 m sec and the switches MS1 MS4 and SW4 are sampled. More particularly, the data of the switches MS1 - MS4 and SW4 is inputted from the switch input circuit 3 and stored in the random access memory 14, and is compared with the data previously sampled. As a result, in case where there is no change, MODE CHANGE flag (Fig.

12) is reset in the random access memory 14 and is returned to the main program, and in case where there is some change, MODE CHANGE flag is set and the general timer 5 is made to be set to 32 m sec and then a program returns to the main program.

The interrupt processing INT1 shown in Fig. is now described briefly, although the detail will be described subsequently. The interrupt INT1 is made for each 1/10 second when the chronograph counter 201 starts. The processing is that 1 is added to the data of 1/10 second in the chronograph data in the random access memory 14, and if there is a carry, a carry to the data of the second in the chronograph data is made and if there is a further carry, a further carry to a more significant digit is made, and the like.

If and when the mode is a chronograph mode and is not in the lap state, the chronograph data is displayed by a display instruction and a program returns to the main program.

The interrupt processing INT2 shown in Fig. 16 is derived from a reference signal generating circuit 1 every 1/2 seconds and performs a timing processing.

First, the data of 1/2 second flag (Fig. 12) in the random access memory 14 is fetched into the arithmetic and logical unit 12 wherein +1 is added to the data, and it is determined whether the result is "1 " or "2". If it is "1 ", a program returns to the main program. If it is "2", "0" is entered into the 1/2 second flag and a processing by a general timer is made. The processing for a timer is executed only if the timer starts. In case where the timer starts, 1 is subtracted from the data of the second for the timer data in the random access memory 14 and if there is a borrow, 1 is further substracted from the digit larger than the digit of the second and a borrow processing is made.As a result, it is determined whether all of the data of the second, minute and hour become 0, and if so, an instruction for causing an alarm and an instruction for setting an interrupt INT3 are executed and the generation of the alarm sound is outputted to the external terminal ALM so that the generation of an interrupt signal INT3 from the switch input circuit 3 is enabled. Then, 1 is added to the second data of the current time and if there is a carry, a carry processing is made. If there is a carry to the minute digit in the carry processing, a processing for alarm and a processing for snooze are made.In the alarm processing, the data of hour and minute stored in the random access memory 14 and the data of the hour and minute for the current time after carry processing are fetched into the arithmetic and logical unit 12 for each digit and it is determined whether those are coincident with each other. If those are coincident with each other, an instruction for generating an alarm sound and an instruction for setting an interrupt INT3 are executed just as the timer processing.In the snooze processing, it is determined whether there is a snooze request by seeing SNOOZE REQ flag (Fig. 12) in the random access memory 14 and if in the snooze request, 1 is added to the data snooze minute in the random access memory 14 and if the result becomes a predetermined time period, for example, five minutes, an instruction for generating an alarm sound and an instruction for setting an interrupt INT3 are executed and an alarm is again achieved.

Then, it is determined whether a mode flag in the area "17" in the random access memory 14 is in a current time mode, and if in a current time mode, a new current time data carried is displayed, and if in the other mode, a program returns to the main program.

The interrupt processing INT3 shown in Fig. 17 is set in the switch input circuit 3 at the time of generation of an alarm sound and is requested when any of the switches SW1 - SW4 is closed (Fig. 6). In this processing, the generation of the alarm signal outputted from the external terminal ALM in the state control circuit 4 is made to be stopped by an alarm sound stop instruction and if there is a snooze request, a SNOOZE REQ flag is set and at the same time the data of the snooze minutes in the random access memory 14 is set and a program returns. If there is no snooze request, a flashing display of an alarm sound mark AMS (Fig. 1) is stopped and the SNOOZE REQ flag is reset and a program returns.In case where an interrupt INT3 is set, only an interrupt signal INT3 is outputted from the switch input circuit 3 even if any of the switches SW1 - SW4 designated is operated, and thus all of the switch designation are neglected.

The priorities of interrupt processings are in order of INTO, INT1, INT2 and INT3, and are determined by the interrupt control circuit 18 as described in the foregoing. In case of interrupt inhibit, an interrupt processing is made after the inhibit is removed. If the interrupt processings are requested during the stop of the system clock, an operation stop instruction "SCP" is executed after interrupt processing.

As described in the foregoing, according to the present embodiment, it is possible to designate an interrupt processing and a switch operation by using switching of the switches and to restart the operation of the clock generator only if the designated switch is operated. In addition, since a function for switch can be set by a program, there is no restriction in changing a specification and thus a general purpose electronic timepiece can be obtained. Furthermore, a consumed electric current is largely reduced since a system operation is being stopped except a necessary time period.

Now, the chronograph mode and the interrupt INT1 will be described in detail using Figs. 8, 15 and 18. Fig. 18 is a flow chart for the chronograph mode which is shown in more detail than that in Fig. 13.

Since the data bus DB is connected to the decoder 15 when the mode becomes a chronograph mode, the chronograph data of the digit larger than the digit of the 1/10 second stored in the areas "00" to "06" (Fig.

12) in the random access memory 14 is sent out to the data bus DB and converted in the decoder 15 to be displayed, Next, an instruction for connecting the chronograph data bus CDB to the decoder 15 is executed, the data bus switching signal DBCHANGE becomes "1" and thus the chronograph data bus CDB is connected to the decoder 15 and a count data in the counter 201 (Fig. 8) is converted to be displayed. The start and stop of the chronograph are made by the closure of the switch SW1 and the lap and chronograph reset are made by the closure of the switch SW2 and hence, in the switch setting, disclosures of the switches SW1 and SW2 are designated. Subsequently, an operation stop instruction "SCP" is executed and an operation is stopped.

Starting the operation, a MODE CHANGE flag (Fig.

12) in the random access memory 14 is investigated and if there is a mode change request, a program jumps to a program for mode change and if there is no mode change request, a processing corresponding to the case where the switch SW1 or SW2 is closed is performed. On the other hand, the outputs S1 OUT or S2 OUT is outputted from the switch input circuit 3 concurrently with closure of the switch SW1 or SW2, so that the T-type flip-flop 205 or 212 is inverted. More particularly, if and when the switch SW1 is closed when the chronograph is in a reset state, the output from the T-type flip-flop 205 becomes "1" and thus the counter 201 starts, and if the switch SW1 is closed during measuring, the output from the T-type flip-flop 205 becomes "0" and thus the counter 201 stops.When the switch SW2 is closed during measuring, the output LAP from the T-type flip-flop 212 becomes "1" and thus rewriting of the digit of the 1/100 second in the latch circuit 16 is stopped and becomes in a lap state.

Furthermore, if and when the switch SW2 is closed in a reset state and a stop state, the output LAP from the T-type flip-flop 212 becomes "0" and in this case, the chronograph is reset by a program processing.

A processing program corresponding to a switch operation determines the state of the chronograph counter 201 and makes a lap display or reset. First, it is determined whether or not the chronograph is in a reset state by seeing a CHRONO RESET flag (Fig. 12) in the random access memory 14, and if it is "0" what the flag is "0" is stored in the random access memory 14. On the other hand, if the CHRONO RESET flag is "1", it is determined whether an output signal START from the T-type flip-flop 205 is "1". If it is "1", the CHRONO RESET flag is set to "0" since the chronograph has been started the time of closure of the switch SW1, and if it is "0", a reset program for chronograph is again performed since the switch SW2 is closed.After setting the CHRONO RESET flag to "0", it is determined whether or not the output signal LAP from the T-typeflip-flop 212 is "1" and if it is "i", it is determined whether or not the previous state is in a stop state by seeing the CHRONO STOP flag (Fig. 12) in the random access memory 14 since the switch SW2 is closed. If the CHRONO STOP flag is "1", the program jumps to a chronograph reset program and if the flag is "0", the LAP flag (Fig. 12) in the random access memory 14 is set to "1" since it is in the lap state, and the CHRONO STOP flag is again set to "0" and a program proceeds.If the output signal LAP from the T-type flip-flop 212 is "0", the LAP flag in the random access memory 14 is set to "0" and it is determined whether or not the output signal START from the T-type flip-flop 205 is "1", since the switch SW1 is closed in the stop state. If it is "1", which means a start state, the CHRONO STOP flag is set to "0" and if it is "0", which means a stop state, the CHRONO STOP flag is set to "1". If and when a chronograph counter reset instruction and a lap reset instruction are executed in the chronograph reset program, the reset signal CHRRESET and LAPRESET (Fig. 7B) become "1", and thus the counter 201, the T-type flip-flop 205, the D-type flip-flop 214 and the T-type flip-flop 212 are reset.The data of the digit larger than the digit of 1/10 second in the random access memory 14 is stored as "0" and the CHRONO RESET flag and the LAP flag in the random access memory 14 are set to "1" and "0", respectively.

Next, a chronograph display program is executed.

First, it is determined whether the output signal LAP from the T-type flip-flop 212 is "1" and if it is "1", the output signal LAPSAMPL from the D-type flip-flop 214 is investigated. If and when the output signal LAP is "0" or the output signal LAP is "1" and the output signal LAPSAMPL is "0", the display for the digit larger than the digit of 1/10 second is displayed from the random access memory 14.Since, in the latter case, the output from the NOR gate 210 is applied to the clock terminal I of the D-type flip-flop 214 through an inverter, the output from the NOR gate 210 is "1" even if a signal LAP becomes "1", that is, the D-type flip-flop 214 is not inverted unless the interrupt signal INT1 is outputted and hence, in this case, the data of the digit larger than the digit of 1/10 second can be displayed since an addition processing on the digit larger than the digit of 1/10 second is not made even if the signal LAP "1". In the display of the data of the digit larger than the digit of 1/10 second, a chronograph data bus CDB continues to be connected to the decoder 15 by a data bus switching instruction executed prior to the switch setting and thus the display of the data of the digit of the 1/100 second continues to be displayed during execution of a program so far described. However, if an instruction for displaying the data of the digit larger than the digit of 1/10 second in the random access memory 14 is executed, the output from the NOR gate 216 becomes "1" and thus the data bus switching signal DBCHANGE becomes "0" and the data bus DB is connected to the decoder 15 so that the data of the digit larger than the digit of 1/10 second is displayed.If the display instruction is terminated, the output from the NOR gate 216 becomes again "0" and thus the chronograph data bus CDB is again connected to the decoder 15 so that a program jumps to the switch setting. If the signal LAPSAMPL is "i", a lap display is held by not displaying the data of the digit larger than the digit of 1/10 second, but jumping to the switch setting since a carry processing is terminated by an interrupt processing INT1.

The interrupt processing INT1 shown in Fig. 15 will be described in detail using Fig. 8. The interrupt processing signal INT1 is an output of the flip-flop 211 which is set in response to a falling edge of a 1/10 second signal outputted every 1/10 second from the time when the counter 201 starts to count a 1/100 second signal through a start of a chronograph. In the interrupt processing INT1, "1" is added to the chronograph data (Fig. 12) in the 1/10 second digit in the random access memory 14 and if there is a carry, a carry processing to a larger digit is performed.

Then, it is determined whether or not a mode is a chronograph mode by seeing a mode flag in the area "17" in the random access memory 14, and if it is not a chronograph mode, a return instruction is executed and a program returns to the main program.

On the other hand, if it is a chronograph mode, a chronograph display program is executed. The chronograph display program is the same as the program shown in a dotted line in Fig. 18. More particularly, if a signal LAP is "0", the data of the digit iargerthan the digit of 1/10 second is displayed and if the signal LAP is "1", the signal LAPSAMPL is determined. At that time, if the signal LAPSAMPL is "0", which means that the state becomes a lap state during interrupt processing, the data of the digit larger than the digit of 1/10 second carried is displayed and if the signal LAPSAMPL is "1", which means that the state became a lap state prior to that interrupt processing, no display is made.The data bus DB is connected to the decoder 15, as described in the foregoing, during execution of the display instruction of the data of the digit larger than the digit of 1/10 second in the display program. After termination of the display program, a return instruction is executed and a program returns.

In case where a chronograph function is added to an electronic timepiece of a central processing unit system in which a timing operation is performed by a program processing, a counter directly controlled by a switching signal of a switch is provided for measuring the 1/100 second digit. The measuring operation of the data of the digit larger the digit of 1/10 second is processed by a program by using an interruption of signal outputted from the counter every 1/10 seconds, and furthermore, in the chronograph mode, the measured data from the counter is always applied to the decoder so that the data bus DB is connected to the decoder only if an instruction for displaying the data of the digit larger than the digit of 1/10 second is executed.Accordingly, the display and measuring of the data of the 1/100 second digit can be precisely made and there is an advantage that a program for chronograph becomes shorter and is simplified.

In the above described embodiment, interrupt processing INTO to INT3 necessaryfortiming operation were used as an interrupt for removing the stop of operation of the clock generator. However, this may be adapted such that the stop of operation of the clock generator is removed in response to a general interrupt factor, for example, an interruption from a timer and thus it is not intended that the interrupt factors are restricted to the present embodiments.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.

Claims (18)

1. An electronic timepiece comprising a reference signal generating circuit (1); a clock generator (2) for generating clocks for system operation based on reference signals from said reference signal generating circuit (1); and a processor (CPU) operating in response to the clocks from said clock generator (2) and including a read only memory (7) in which a program is written in a fixed manner and a random access memory (14) for storing data, characterized in that said electronic timepiece comprises means (4, 186, 128, 126) for stopping the operation of said clock generator (2) when a predetermined instruction (SCP) of the program written in said read only memory (7) is executed, and means (130,127,126) in response to occurrence of interrupt for removing the stop of operation of said clock generator (2).

2. An electronic timepiece in accordance with claim 1, which further comprises operating switches (SW1 - SW4), operation detecting means (3, 157) for detecting operation of said operating switches (SW1 - SW4), and means (127,126) in response to a signal (CLK START) from said operation detecting means for removing the stop of operation of said clock generator (2).

3. An electronic timepiece in accordance with claim 1 or 2, which further comprises timer means (5,113) for measuring a predetermined time period, and means (127, 126) in response to a timer output (GTIMER OUT) from said timer means for removing the stop of operation of said clock generator (2).

4. An electronic timepiece in accordance with any one of claims 1 to 3, which further comprises means (185) for detecting termination of an interrupt processing, means (243, 20,8) in response to a signal (RTS) from said means (185) for setting an address of said read only memory (7), and means (241, 19, 9, 20) in response to termination of an interrupt which is caused when an operation of said clock generator (2) is stopped, for setting as said address the same address as that at the time when the interrupt was caused.

5. An electronic timepiece in accordance with claim 4, which further comprises means (241, 19,9, 20) in response to termination of an interrupt which is caused during an operation of said clock generator (2), for setting as said address an address subsequent to that at the time when the interrupt was caused.

6. An electronic timepiece in accordance with claim 1, which further comprises a plurality of switches (SW1 - SW4) connected to a plurality of external terminals (S1 - S4), a switch input circuit (3) accepting switching signals of said switches from said external terminals, setting means (4, 170) for providing signals (SWCON, S1 UP - S4 DOWN) setting any state to said switch input circuit, and means (147, 148, 157) for generating a signal (CLK START) starting an operation of said clock generator (2) in response to the fact that a corresponding switch set by said signal is made to be in a corresponding state.

7. An electronic timepiece in accordance with claim 6, which further comprises means (4, 188,sow LOCK, 166, 160) for setting an interrupt in said switch input circuit (3) so that an interrupt is caused therefrom in response to the operation if and when the switch is operated, and means (162 - 165) in response to an operation of said switch for generating a interrupt signal (INT3) if and when an interrupt is set by operation of said switch.

8. An electronictimepiece in accordance with claim 7, which further comprises means (146, 155) for invalidating signals from the switches operated if and when an interrupt is set by operation of said switch.

9. An electronic timepiece in accordance with claim 1, which further comprises a chronograph counter (6, 201) in response to signals (1/100 sec) from said reference signal generating circuit (1) for counting the unit of 1/100 second, means (209 - 211) for periodically generating an interrupt signal (INT1) during counting operation of said chronograph counter, and means (CPU, 12,13) in response to said interrupt signal for accummulating in said random access memory (14) time data of the unit larger than the unit of 1/10 second.

10. An electronic timepiece in accordance with claim 9, which further comprises a decoder (15) for display, a chronograph data bus (CDB) to which the count data is outputted from said chronograph counter (201), a data bus (DB) to which said time data accumulated in said random access memory (14) is outputted, and means (204, 202, 203) in response to a predetermined instruction (CDB to DEC, DBUSENA) of the program for selectively connecting one of said chronograph data bus (CDB) and said data bus (DB) to said decoder (15).

11. An electronic timepiece in accordance with claim 9 or 10, which further comprises a switch (SW1) for controlling operation of said chronograph counter (201), a flip-flop (205) being inverted in response to a signal (S1, OUT) from said switch (SW1), and means (206) in response to an output from said flip-flop for controlling application of said signal (1/100 sec) into said chronograph counter.

12. An electronictimepiece comprising a reference signal generating circuit (1); a clock generator (2) for generating clocks for system operation based on reference signals from said reference signal generating circuit (1); a processor (CPU) operating in response to clocks from said clock generator (2) and including a read only memory (7) in which a program is written in a fixed manner and a random access memory (14) for storing data; a data bus (DB) coupled to said processor for providing a data to said random access memory and withdrawing the data therefrom; and displaying means (15, 16) for displaying the data fed to said data bus, characterized in that said electronic timepiece comprises a chronograph counter (201) operating upon receipt of periodic signals (1/100 sec) from said reference signal generating circuit, means (209 - 211) for periodically generating interrupt signals (INT1) during operation of said chronograph counter, and means (12,13) in response to said interrupt signal foraccummulating in a predetermined area of said random access memory time data of the unit larger than the unit of 1110 second of passing time.

13. An electronic timepiece in accordance with claim 12, which further comprises a chronograph data bus (CDB) for directly providing the count data of said chronograph counter (201) to said displaying means (15, 16).

14. An electronic timepiece in accordance with claim 13, which further comprises means (202 - 204) in response to a predetermined instruction (CDC to DEC, DBUSENA) of said program for selectively connecting said data bus (DB) or said chronograph data bus (CDB) to said displaying means (15, 16), whereby in the chronograph mode the count data of said chronograph counter (201) is applied to said displaying means (15,16) exceptforthedata of the unit larger than the unit of 1/10 second of passing time.

15. An electronic timepiece in accordance with any one of claims 12 to 14, which further comprises a switch (SW1) for controlling operation of said chronograph counter (201), a flip-flop (205) being inverted in response to a signal (S1 OUT) from said switch (SW1), and means (206) in response to an output from said flip-flop for controlling application of said signal (1/100 sec) into said chronograph counter.

16. An electronic timepiece in accordance with claim 14, wherein said displaying means includes a latch circuit (16), and which further comprises a switch (SW2), and a flip-flop (212) being inverted in response to a signal (S2 OUT) from said switch (SW2), rewriting of data in said latch circuit (16) being inhibited in response to an output (LAP) from said flip-flop (212).

17. Amicroprocessor-controlled electronictime- piece in which the microprocessor is operable to execute an instruction which causes the operation of the microprocessor to be halted, the microprocessor being responsive when halted to an interrupt signal which causes the microprocessor to execute an interrupt routine.

18. An electronic timepiece substantially as herein described with reference to the accompanying drawings.