JPS598794B2 - Densito Kei Cairo - Google Patents

Description

[Detailed description of the invention] The present invention relates to improvements in electronic timepiece circuits.

FIG. 1 shows a conventional example of this type of electronic timepiece circuit.

In the figure, 1 is a signal generator that generates a reference frequency signal 10, for example, by frequency-dividing a signal obtained from a crystal oscillator.
1 (Hz) accurate reference frequency signal 10 is generated.

11 is a second counting circuit that counts the reference frequency signal 10 and
A second signal 110 corresponding to 59 seconds is generated from 0 seconds, and a carry signal 111 is generated when this second signal 110 changes from 59 seconds to 00 seconds.

This carry signal 111 is a signal with a period of one minute.

12 is a minute counting circuit which counts the carry signal 111 and outputs a minute signal 120 corresponding to 59 minutes from 00 minutes, and also generates a carry signal 121 when the minute signal 120 changes from 59 minutes to 00 minutes.

This carry signal 121 is a one-hour period signal.

13 is a clock circuit that counts the carry signal 121 and outputs OO.
A time signal 130 corresponding to 23:00 is generated, and a carry signal 131 is output when the time signal 130 changes from 23:00 to 00:00.

This carry signal 131 is a signal with a daily cycle.

14 is a day counting circuit that counts the carry signal 131 and returns it to 01.
A day signal 140 corresponding to 31 days from the day is output.

Each signal 110, 120, 130, 140
are sent to, for example, a liquid crystal display and used to digitally display seconds, minutes, hours, and days, respectively.

In this way, conventional electronic clock circuits use separate counting circuits to display seconds, minutes, hours, and days, and in order to display including the day as in the example above, a total of 4 counting circuits are used. One counting circuit 11-14 is required.

This counting circuit is constructed using, for example, a flip-flop, but it requires the use of a large number of circuit elements.
Even when an integrated circuit is configured including this, most of the integrated circuit ends up being occupied by the counting circuit.

In a conventional electronic timepiece circuit that includes a stopwatch circuit, a second counting circuit 15 is added that counts the reference frequency signal 10 shown in FIG.
Counting the reference frequency signal 10 during a period in which 0 is given,
Outputs a second signal 150.

In this conventional circuit as well, since the second counting circuit 15 is added separately from the other counting circuits 11 to 14, the counting circuit becomes large.

The present invention proposes an electronic timepiece circuit whose circuit configuration is simplified by utilizing one counting circuit to output at least two mutually different signals.

FIG. 2 shows a first embodiment of the inventive circuit.

This embodiment is configured to be implemented using the four counting circuits shown in FIG.

In the figure, 1 is a signal generator that generates an accurate reference frequency signal 10 of 1 (Hz), and 20 is a counting circuit that generates the reference frequency signal 1.
In addition to the input terminal ■ which receives 0, there is an output terminal Q1 which generates an output signal 210, an output terminal 0 which outputs a carry output signal 211, a data input terminal D which receives a data signal 021,
It has a reset terminal R1 for receiving the IJ set signal 405, a command input terminal L1 for receiving the data input command signal 406, and an input terminal B for receiving the memory signal 310.

This counting circuit 20 has a first function of counting the reference frequency signal 10, a second function of resetting the count value by a reset signal 405, and a data input command signal 406 to the command input terminal L. A third function that receives input and presets it, and the above data signal 0.
It has a fourth function of adding 1 to the preset data signal value based on the memory signal 310 after the preset of 21.

31 is a first memory circuit, which outputs a carry output signal 211
This memory is stored as a memory signal 31.
It is configured to output as 0, and the stored contents can be erased when the reset signal 031 is received at the R2 terminal.

32 to 35 are second memory circuits, each of which has a counting circuit 20;
In response to the output signal 210 of the output signal 320, 330,
340, 350, are output.

The output signals 320, 330, 340, and 350 are used as a second signal, a minute signal, an hour signal, and a day signal, respectively, and are sent to a digital type display (not shown).

51 to 54 are output signals 320, 330, 340, and 3, respectively.
50 and outputs any of these output signals as data signal 02.
Switch circuits 61 to 64 are judgment circuits that receive and judge the output signals 320, 330, 340, and 350, respectively.The judgment circuit 61 outputs 60 seconds, that is, 00 seconds, and the judgment circuit 62 outputs 60 The determination circuit 63 determines 24 o'clock, i.e., 00 minutes, and the determination circuit 64 determines 32 o'clock, i.e., 00 minutes.
output signals 610, 620,
630,640 are generated.

40 is the output memory signal 310 of the memory circuit 31 and the judgment output signals 61 0 , 620 , 620 of the judgment circuits 61 to 64;
630 and 640, the control signals 401 and 40
2, 403, 404, a reset signal to the counting circuit 20, 405, and a control circuit that generates a data input command signal 406.

R3 is a reset terminal that receives the reset signal 041.

The control signals 40 1 , 402 , 403 and 404 respectively control the storage timing of the second memory circuits 32 - 35 and also control the closing timing of the switch circuits 51 - 54 .

In Figure 2, in order to avoid complication of the drawing,
Wiring related to the DAROC signal and power supply voltage that control the timing of the entire system is omitted.

FIG. 3 shows a specific example of the configuration of the counting circuit 20.

221-226 in the figure are JK flip-flops, 231-226
242 is an AND circuit, 251 to 257 are inverters, 2
61 and 262 are NAND circuits, 271 is an OR circuit, 28
0 to 299 are NOR circuits.

This is a 64-decimal counting circuit, and outputs a 6-bit output signal 210 at six output terminals Q1 to Q6.

In line with this, there are also 6 input terminals D1 for data signal 021.
~D6 is provided.

The memory signal 310 to the terminal B is normally at L level, so the reference frequency signal 10 to the terminal (2) passes through the AND circuit 231 and is applied to the T terminal of each JK flip-flop 221 to 226 through the OR circuit 271. In this state, each flip-flop counts the reference frequency signal 10.

Flip-flops 221 to 226 sequentially perform counting operations at the 16 frequencies of the previous flip-flop, and the weights of flip-flops 221 to 226 are 1, 2, and 1, respectively.
4, 8, 16, 32.

If the outputs of the terminals Q1 to Q6 are combined by the NOR circuit 280, an H level output is obtained at the output terminal O when 00 is counted.

When the reset signal 405 to i-child R1 becomes H level,
The reset terminal R of each flip-flop 221-226 becomes H level, and each flip-flop 221-226 is reset.

When the data input command +-406 to the command input terminal L goes to H level, the data signal 021 to the terminals D1 to D6 goes to each JK
The data signal 021 is applied to the JK terminal of flip-flops 221 to 226, and when one clock is applied to the T terminal of each flip-flop 221 to 226 in this state, the data signal 021
is preset in each flip-flop 221-226.

In this state, when one clock is further applied to the T terminal of each flip-flop, the counting circuit 20 adds and counts the value of the preset data signal 021 plus 1.
An additional count output of (data signal value +1) is generated at Q1 to Q6.

The clock for presetting and the clock for additional counting are connected from clock terminal C to AND circuit 232 and O when memory signal 310 to terminal B becomes H level.
Each flip-flop 221 to 22 is connected through an R circuit 271.
It is given to the T terminal of 6.

FIG. 4 shows a specific example of the configuration of the control circuit 40. As shown in FIG.

In the figure, 411, 412, 413, 414 are D flip-flops, 421 is an inverter, and 431 to 433 are NANs.
D circuit, 441 is an OR circuit, and 451 is an AND circuit.

Judgment output signals 610 to 640 are applied to the D terminals of D flip-flops 411 to 414, respectively, and are input to an OR circuit 441.

The reset signal 405 is output as an OR output of the determination output signals 610 to 640.

The clock from the clock terminal C is applied to the T terminal of each flip-flop 411-414, and the reset signal 041 to the reset terminal R3 is applied to each of the reset terminals R.

By applying the Q output of flip-flop 411 to inverter 421, control signal 401 is applied, and by applying the outputs of flip-flops 411 and 412 to NAND circuit 431, control signal 402 is applied to
By applying the Q output of 2,413 to the NAND circuit 432, the control signal 403 is further applied to the flip-flop 413.
, 414 to a NAND circuit 433, a control signal 404 is generated, respectively.

AND circuit 451 connects memory output 310 of memory circuit 31
Then, in response to the carry signal 211 of the counting circuit 20, the data input command signal 406 is generated.

Now, the operation of the embodiment shown in FIG. 2 will be explained.

First, if the output signal of the output terminal Q of the counting circuit 20 is an output corresponding to 1 to 59 seconds, the outputs 401 to 401 of the control circuit 40
Among the signals 406, only the output signal 401 becomes H level, and therefore the memory 32 sequentially stores and outputs the output signal 210 of the terminal Q.

In this state, the second signal output 320 from the memory circuit 32
only changes in accordance with the counting operation of the reference frequency signal 10 by the counting circuit 20.

The memory circuits 33 to 35 respectively store and output minute, hour, and day signals at that time.

The output 210 of the terminal Q of the counting circuit 20 becomes a signal corresponding to 60 seconds or OO seconds every minute, and each time this reaches 60 seconds or OO seconds, it becomes a signal corresponding to 1 second until the next 01 seconds. The necessary carry operations are performed during the second period.

This carry operation includes a first operation that resets the contents of the memory 32 to 00 seconds, and a second operation that carries the contents of the memory 33.
operation, memory 3 if necessary depending on the contents of memory 33.
This includes a third operation of carrying up the contents of 4 and a fourth operation of carrying up the contents of memory 35 if necessary depending on the contents of memory 34.

Generally speaking, in the first operation, when the output 210 of the counting circuit 20 becomes a signal corresponding to 60 seconds, the determination output 610 of the determination circuit 61 becomes H level, thereby triggering the reset signal 405. This reset signal 4
This is an operation in which the counting circuit 20 is reset by 05, the signal 210 is made a signal corresponding to 00 seconds, and this signal 210 is stored in the memory 32 based on the control signal 401.

When the output 210 becomes a signal corresponding to 60 seconds, the control signal 401 becomes L level, the control signal 402 becomes H level, and when the output 210 becomes a signal corresponding to 00 seconds, a carry signal 211 is output. be done.

The second operation is performed by using the control signal 4 after the first operation.
02, the content of the memory 33, that is, the minute signal, is outputted as a data signal 021 through the switch circuit 52, and this is preset in the counting circuit 20 based on the data input command signal 406, and then carried up in the first operation. signal 2
Based on the output of 11, the counting circuit 20 performs an additional count of adding 1 to this preset value, and after performing this additional count, the minute signal obtained as the output 210 is stored in the memory based on the control signal 402. 33.

After performing additional counting in this second operation, the output 2
When the minute signal obtained as 10 minutes becomes a signal that overlaps with 60 minutes, the determination output 620 of the determination circuit 62 becomes H level to generate the reset signal 405 again, and this reset signal 405 resets the counting circuit 20. , after converting the contents into a signal corresponding to the OO minutes, this signal corresponding to the 00 minutes is stored in the memory 33 based on the control signal 402.

When the output 210 becomes a signal corresponding to 60 minutes,
Based on the determination output signal 620, the control signal 402 becomes L level, the control signal 403 becomes H level, and the output 210
When becomes a signal corresponding to 00 minutes, carry signal 21
1 comes out.

The third operation is performed by controlling the control signal 403 by the second operation.
is at H level, the content of the memory 34, that is, the time signal, is outputted as the data signal 021 through the switch circuit 53 based on the control signal 403, and a carry signal 211 is outputted by the previous second operation. If so, a data input command signal 406 is output, and when the signal is output through the switch circuit 53, the signal is preset in the counting circuit 20, and an additional count of +1 is performed on this preset value. Output 21 of counting circuit 20
0 is stored in the memory 34 based on the control signal 403.

When the output 210 after the additional counting becomes a signal corresponding to 24 o'clock, the determination output 630 of the determination circuit 63 becomes H level, so that the reset signal 405 is generated again, and the counting circuit 20 is reset by this reset signal 405. After converting the contents into a signal corresponding to 00 o'clock, this signal corresponding to OO o'clock is stored in the memory 34 based on the control signal 403.

When the output 210 becomes a signal corresponding to 24 o'clock,
Based on the determination output signal 630, the control signal 403 becomes L level, the control signal 404 becomes H level, and the output 21
If 0 becomes a signal corresponding to OO, carry signal 211
becomes H level.

In the fourth operation, the control signal 404 goes high due to the third operation.
This occurs when the control signal is at the level 40.
4, the content of the memory 35, that is, the date signal, is output as the data signal 021 through the switch circuit 54, and if the carry signal 211 has been output by the previous third operation, the data input command signal 406 is output, and the switch circuit 54 outputs the data input command signal 406. circuit 5
The day signal output through 4 is preset in the counting circuit 20, and an additional count of 1 is added to this preset value.
The output 210 of 0 is stored in the memory 35 by the control signal 404.

When the output 210 after additional counting becomes a signal corresponding to the 32nd day, the judgment output 640 of the judgment circuit 64 becomes H level,
As a result, the reset signal 405 is generated again, the counting circuit 20 is reset by the reset signal 405, the output 210 is made into a signal corresponding to day 01, and this is stored in the memory 35 based on the control signal 404.

The first to fourth operations described above are configured so that they are all completed within a period of usually 20 clocks after the output 210 becomes a signal corresponding to 60 seconds, and after this, the control circuit 40 is Signals 401 to 406 by reset signal 041
During this period, only the signal 401 returns to the H level, and the counting circuit 20 prepares for counting the reference frequency signal 10.

This signal 10 becomes H level again after a period of 60 clocks has elapsed after it became L level, and the first to fourth operations described above are completed within this period. be made to do.

Next, the operation of the embodiment shown in FIG. 2 will be explained using FIG. 5, which is a timing chart.

Waveform A in FIG. 5 is a clock waveform that controls the timing of this system.

All operations are synchronized to this clock timing.

A reference frequency 10 from a reference frequency generator 1 is shown at the waveform opening.

Now, when signal 10 is at H level (the leftmost position in the figure), it is at 8:59:59 on the 2nd, and then signal 10 changes from H level to L level for 60 seconds (at 9:00 on 2nd). hour 0
0 minutes 00 seconds).

At this time, before 60 seconds, the signal 401 waveform is at H level, the output 210 of the counting circuit 20 is stored in the memory 32, and the unchanged output becomes the output signal 320, indicating 59 seconds.

This second signal 320 also serves as the data signal 021 of the counting circuit 20, but since the waveform nu of the data input command signal 406 is at the L level, it is not input to the counting circuit 20, and is not input to the counting circuit 20.
0 is counting signal 10.

Also minute signal output 330, hour signal output 340, day signal output 3
50 are memory circuits 33, 34 . 35, in this case, signals of 59 minutes, 8 o'clock, and 2 days, respectively, are output.

Now, let us consider the case where the signal 10 changes from the H level to the L level for 60 seconds.

The timing at this time is assumed to be the 0th timing in the Kurotsukui waveform.

In this case, since the signal 320 has increased by 60 seconds, the output 610 of the determination circuit 61 goes from the L level to the H level, and accordingly, the reset signal output 405 of the control circuit 40 goes to the H level at the first clock, and the counting circuit 20 Reset.

The resulting signals 210 and 320 indicate OO seconds.

(Refer to waveform L and force) At the same time, the carry signal 211 changes from L level to H level as shown in waveform 2, and the signal 310 changes from L level to H level as shown in waveform E.

In this case, the control signal 401 of the second clock timing control circuit 40 changes from the H level to the L level, and conversely, the control signal 401 of the second timing control circuit 40 changes from the H level to the L level.
02 goes from L level to H level.

However, the signals 403 and 404 remain at L level.

In this state, the memory circuit 32 stores 00 seconds and stops new memory operations, so even if the signal 210 changes to become a minute signal, the contents stored in the memory 32 do not change.

Therefore, the seconds signal 320 remains at OO seconds as shown in the waveform force.

However, the signal 401 changes from the H level to the L level.
2 changes from L level to H level, switch 51 is turned off and switch 52 is turned on, and the signal in memory circuit 33 (state is 59 minutes) becomes data signal 021 to counting circuit 20.
In response to the command signal 406 shown in waveform N going high, the third clock timing counting circuit 20
A 9 minute signal is input and preset.

Next, this counting circuit 20 is now preset with data, and when the output of the memory circuit 32 is at the H level, it is added to count by 1 clock, so the next 5 clocks are counted.
The counting circuit 20 at the th clock timing performs additional counting of this one clock.

This means that the output 210 of the counting circuit 20, which is preset with a signal for 59 minutes, becomes a signal corresponding to 60 minutes (
As in the case of 60 seconds, the output 620 of the determination circuit 62 changes from L level to H level at the 6th clock timing, the reset signal 405 becomes LL level again, and the counting circuit 20 is reset. Ru.

Since the memory circuit 31 is set by the periodic reset signal 031, in this case it is reset at the fifth timing of the clock, and the output 310 of the memory circuit 31 changes from the H level to the L level.

It is clear that the output 330 at this time indicates 00 minutes.

Then, at the seventh clock timing, the output 402 of the control circuit 40 changes from H level to L level, and the output 403 changes from L level to H level.

At this time, the switch 52 is closed and the switch 53 is opened, and the contents of the memory circuit 34 become the data input 021 to the counting circuit 20.

(The content starts at 8 o'clock).

Data input command 4>406 at the 8th clock timing
changes from the L level to the H level, and in response, the data input signal 021 is preset in the counting circuit 20.

At this time, the output 210 of the counting circuit 20 indicates 8 o'clock.

Furthermore, since the output 310 of the memory circuit 31 is at the H level, the counting circuit 20 performs an additional count of one clock, and the output signal 210 becomes the state of 9 o'clock.

Even in this case, the determination circuit 63 remains at the L level, and furthermore, at timing No. 10, the output 3 of the memory circuit 31
10 goes from H level to L level (waveform wa).

At the 12th timing, output 610-640, output 3
10 is at L level, the output 403 of the control circuit 40
changes from H level to L level, and output 401 returns from L level to H level.

In this case, the outputs 320 to 350 are 00 seconds, 00 minutes, and 9
There is no change in the fact that the time is 2 days, and this is the same in the case of the conventional circuit, so there is no change in power consumption.

FIG. 6 shows another embodiment of the invention.

This embodiment is an electronic timepiece circuit having a stopwatch function. Simply put, a counting circuit that normally counts a day signal performs the counting function of a stopwatch.

Signal generator 1, seconds, minutes, hours counting circuit 11, 12, 1
3 outputs a second signal output, a minute signal output, and an hour signal output 1 1 0, 120, and 130 as in FIG.

36 is a memory circuit that stores the carry output 131 of the clock counting circuit 13, and has a reset terminal R2 that receives a reset signal 036.

24 is a counting circuit similar to the counting circuit 20 shown in FIG. 2, and has an input terminal (2), a reset terminal R1, a data input terminal D1, a data input command terminal L, and an output terminal Q.

37 is another memory circuit, which converts the output signal 240 from the counting output terminal Q of the counting circuit 24 into the stopwatch signal 1.
60.

55 is a switch circuit, which also receives stopwatch signal 1.
60 outputs a data input signal 024 to the counting circuit 24.

65 determines the output 240 of the counting circuit 24 and also determines the signal 1
60, a reset signal 650 is sent to the reset terminal R1.
occurs.

This has a function to determine 60 seconds and a function to determine 32 days.

71 is a switch circuit between the memory circuit 36 and the input terminal ■; 81 is a start/stop switching circuit;
It receives the signal 10 and the start/stop signal 081- from the switch circuit 71, and outputs an output signal 810 to the switch circuit 71.

The output signal 810 becomes a seconds signal when starting, and is fixed at L level when stopping.

The stopwatch signal 160 is also applied to the data input command terminal L1 of the counting circuit 24 and the switch circuit 71.

Note that the switch circuit 71 outputs 360 in response to the signal 160.
In normal clock operation, the carry signal 131 of the clock counting circuit 13 once stored in the memory circuit 36 is transferred to the switch circuit 71.
A counting circuit 24 performs counting, and its output 240 is a date signal.

When the stopwatch signal 160 becomes H level and a stopwatch command is issued, the output 240 of the counting circuit 24 at that time is stored in the memory circuit 37, and the determination circuit 65 outputs a reset signal 650, and the counting circuit 2
Reset 4.

At the same time, when the signal 160 becomes H level, the switch 71 is switched, and the output 810 is coupled to the input terminal (2) of the counting circuit 24 instead of the output 360.

When the start/stop signal 081 becomes a start and the start of the stopwatch operation is instructed, the signal 810 becomes a seconds signal, which is counted by the counting circuit 24.

When the signal 081 becomes stop and the stopwatch is instructed to stop, the signal 810 becomes L level, the counting operation of the counting circuit 24 is stopped, and the second signal counted by the stopwatch is outputted by the signal 240, which is displayed on the display. Is displayed.

Note that the output 240 is 6 during the stopwatch timing period.
When the time reaches 0 seconds, the determination circuit 65 outputs a reset signal 650 to set the counting circuit 24 to 00 seconds.

Next, when returning to the normal timekeeping operation, the signal 160 is set to L level.

As a result, the stored content (date signal) of the memory circuit 37 is applied to the data input terminal D of the counting circuit 24 through the switch 55, and is preset in the counting circuit 24.

When a carry signal 131 is output from the clock circuit 13 during use as a stopwatch (this is what happens when the watch is used as a stopwatch at midnight), the memory circuit 36 stores this carry signal 131 and returns to normal timekeeping operation. When the contents of the memory 37 are preset in the counting circuit 24, the counting circuit 24 performs one additional count.

When the output 240 of the counting circuit 24 becomes a signal corresponding to the 32nd day, the signal 650 becomes H level, the counting circuit 24 is reset, and the output 240 becomes a signal corresponding to the 1st day.

In the embodiment of FIG. 6, there is no need to add a special counting circuit for the stopwatch function.

As described above, according to the circuit of the present invention, the required functions can be performed using fewer counting circuits, and a small and inexpensive electronic timepiece circuit can be realized.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional circuit, Fig. 2 is a block diagram showing an embodiment of the inventive circuit, Figs. 3 and 4 are circuit diagrams showing details of its main parts, and Fig. 5 is an operation timing. The chart diagram and FIG. 6 are block diagrams showing other embodiments of the circuit of the present invention. In the figure, 1 is a signal generator, 11, 12, 13, 14, 20,
24 is a counting circuit, 31 to 37 are memory circuits, 40 is a control circuit, 51 to 55 are switch circuits, 61 to 65 are determination circuits, 71 is a switch circuit, and 81 is a start/stop switching circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1 Input terminal 1 for receiving a reference frequency signal, output terminal Q for generating an output signal, output terminal O for outputting a carry output signal, data input terminal D for receiving a data signal, and reset terminal R1 for receiving a reset signal. , a command input terminal L for receiving a data input command signal, and an input terminal B for receiving a memory signal, and a first function for counting the reference frequency signal supplied to the input terminal (2), and the reset terminal R1. a second function of resetting the count value by a reset signal to the command input terminal L; a third function of receiving and presetting the input of the data signal by a data input command signal to the command input terminal L; a counting circuit having a fourth function of adding plus 1 to the preset data signal value based on the memory signal supplied to the input terminal B after presetting, and a carry output signal of this counting circuit; a memory circuit that receives and stores the stored content, outputs the stored content as a memory signal, and erases the stored content when receiving a reset signal at the R2 terminal; receives the output signal of the counting circuit and stores it; A second signal memory circuit that outputs this memory content as a second signal;
A memory circuit for minute signals that receives and stores the output signal of the counting circuit and outputs the stored content as a minute signal; a memory circuit for receiving the output signal of the counting circuit and stores the stored content as an hour signal; A memory circuit for the time signal when outputting, a memory circuit for the day signal that receives the output signal of the counting circuit, stores it, and outputs the stored contents as a day signal, and an output signal when it receives the second signal and determines whether a carry is necessary. A determination circuit for the minute signal that receives the above minute signal and generates an output signal when determining the need for a carry, a determination circuit for the minute signal that receives the above hour signal and generates an output signal when determining the need for a carry. A judgment circuit, a day signal judgment circuit that receives the above date signal and generates an output signal when determining whether a carry is necessary, an output memory signal from the above memory circuit, and a second signal, a minute signal, an hour signal, and a mortar signal. A control signal for receiving each output signal of the determination circuit and controlling the storage timing of the memory circuit for the second signal, minute signal, hour signal, and day signal, and a reset signal and data input command signal for the counting circuit. a control circuit for generating the second signal, a second signal switch circuit that receives the second signal and the second signal control signal of the control circuit and outputs a data signal to the counting circuit, a control circuit for the minute signal and the minute signal of the control circuit; a minute signal switch circuit that receives a signal and outputs a data signal to the counting circuit; a hour signal switch that receives the hour signal and the hour signal control signal of the control circuit and outputs a data signal to the counting circuit; An electronic timepiece circuit comprising a date signal switch circuit that receives the date signal and a date signal control signal from the control circuit and outputs a data signal to the counting circuit.