JPS6011513Y2 - electronic clock device - Google Patents

Description

[Detailed explanation of the idea] The present invention relates to an electronic clock device.

For example, the following electronic clocks are known in the past.

There was one in which an electronic circuit drove a mechanical oscillator to operate a magnetic escapement, driving hands via a wheel train and displaying the time.

However, although this watch uses an electronic circuit as part of the watch, it also includes a mechanical part, so it is prone to breakdowns due to friction, wear, etc., and is also inconvenient when miniaturizing.

Some electronic clocks have also been announced, but these use a frequency converter to step down the output of a crystal oscillator to a low frequency, and a counter generates an output for each time to display the time. there were.

However, this simply replaced the conventional mechanical parts with electronic circuits, and its only purpose was to display the time.

Therefore, the present invention provides an electronic clock device that extracts an audible frequency from a frequency divider that divides the output frequency of a crystal oscillator and generates a sound at a set time, thereby eliminating the defects of the conventional clock.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is a standard signal generator, and in this embodiment a crystal oscillator is used.

2 is a frequency divider that steps down the output of the standard signal generator 1 to the frequency of a desired time signal;
It's descending down to seconds.

The standard signal generator 1 and frequency divider 2 described above constitute a time signal generator.

3 is a running counter, which counts the first time unit of □ seconds.

4 is a hexadecimal counter, which counts time units of w seconds.

5 is a W-adic counter, which counts units of time in the 1st digit of minutes.

6 is a hexadecimal counter, which counts units of time in minutes.

7 is a decimal counter, which counts the time units of the 1st and Wth digits of time.

In this embodiment, the counters 3, 4, . . . 7 constitute a timekeeping device.

Decoder circuits 8, 9, . . . , 12 convert the outputs of the counters 3, 4, . . ., 7.

13.14...17 are counters 3, 4...7 respectively
A desired number of the display element, which will be described later, is selected in accordance with the time measurement output.

For example, it is a numerical pattern selection circuit consisting of a diode matrix.

Reference numerals 18, 19, . . . 22 are display element drive circuits, respectively.

Decoder circuits 8, 9...12, number pattern selection circuits 13.14...17 and drive circuits 18.19...
22 constitutes a time display operating device.

23° 24...27 are drive circuits 18, 19, and 27, respectively.
... is a display element that receives each output of 22 and displays a desired number.

Here, the displayed numbers 23, 24, . . . 27 constitute a time display device.

28, 29...32 are NOR circuits, 33, 34 are NAND circuits, and 35 is an inverter circuit.

81 is a reset/start switch for resetting or starting the frequency divider 2, counters 3, 4, . . . , and contacts 36a1, reset contact 36b1, start contact 36;
It is composed of c.

37 is a counter 5. 6. This is a fast-forward switch for accelerating the counting speed of No. 7, and is composed of a contact piece 37a, a feed stop contact 37b, and a fast-forward contact 37c.

A flip-flop circuit 38 constitutes a part of a drive device for driving an external load.

39 is a transistor, 40 is a speaker, and 41 is a time signal switch, which is composed of a contact piece 41a1 and a contact point 41b.

The transistor 39, the speaker 40, and the time signal switch 1 constitute a time signal device.

(The work is a time setting device of the minute order, 42a is a contact piece,
42b, 42c...42 each have a decoder circuit l.
This is a terminal that receives the output of 0 minutes, 1 minute...9 minutes of O,
421 is an open terminal.

43a is a contact piece, 43b, 43c...43g are terminals that receive the outputs of OC@, 10 minutes...5 powder of the decoder circuit 11, respectively. , 43h are open terminals.

44 is a time setting device for time 1 and 0;
4a is a contact piece, 44b, 44c, .

In the above, the NAND circuit 34 and the time setting devices 42 to 4
4 constitutes a scheduled time output device.

45 is a reset switch of the flip-flop circuit 38, which is composed of a contact piece 45a and a terminal 45b.

In FIG. 2, the horizontal axis shows time t1, and the vertical axis shows the signal magnitude.

Next, the operation will be explained.

Note that the following logical operations will be explained using positive logic.

First, the reset/start switch 11 is connected to its contact piece 36a.
is connected to the start side contact 36c, and the fast-forward switch 11 connects its contact piece 37a to the feed stop contact 37b.

The reset switch 1 and the time signal switch 41 are opened, and the contact piece 42a*4 of the time setting device 42, 43, 44 is opened.
3at 44a is open contact 421 = 431t 44
Connect to rn.

Therefore, when an output is generated from the standard signal generator 1, this is frequency-divided by a frequency divider 2 to lHz and counted by a counter 3.

At the same time that the count becomes river sand, carry is generated and supplied to the counter 4.

A carry occurs when counter 4 counts for 60 seconds, but
This is shaped into an impulse and then supplied to the counter 5 via the NOR circuit 32.

The point of shaping into an impulse shape will be explained in the section regarding the fast-forward operation of the timing device.

Thereafter, in the same manner, the counter 6 counts the minutes and the counter 7 counts the hours.

Now, counters 3, 4...7 each have 4゛', "g 5
99. (4399°462 It, “10°” is counted.

The output of the first digit of seconds passes through the decoder circuit 8, and the number pattern selection circuit 13 selects the number pattern "4" of the display element 23, and the output of the drive circuit 18 outputs 66499 to the display element 23.
Display.

Similarly, the output of the counter 4 is passed through the decoder circuit 9 to the numeric pattern selection circuit 14 which selects the numeric pattern "5" of the display element 24.
Display 5° on 4.

The output of the counter 5 is sent to a display element 25 via a decoder circuit 10, a numeric pattern selection circuit 15, and a drive circuit 20.
Show 3pa.

Similarly, the output of the counter 6 passes through the decoder circuit 11, the numeric pattern selection circuit 16, the selection circuit 16, and the drive circuit 21 to display 2' on the display element 26.

The output of the counter 7 is sent to the display element 27 via the decoder circuit 12, the number pattern selection circuit 17 and the drive circuit 22.
'10' is displayed.

Therefore, 101142'5-54 seconds is displayed on the display device, and the time is thereafter displayed as time passes.

Next, the timed operation will be explained.

- As an example, a case where an external load is driven at 0:12 minutes and seconds will be explained.

First, connect the contact piece 42a of the time setting device n to the 2 minute terminal 42d, and connect the contact piece 43a of the time setting device U to the 0 minute terminal 4.
3c, and connect the contact piece 44a of the time setting device 11 to the 0 o'clock terminal 44b.

When the time reaches 0:12 and 00 seconds, the counter 5 counts 2, the counter 6 counts 1, and the counter 7 counts 0.

Therefore, g 2 t of the decoder circuits 10, 11゜12
t, “1゛66 Q II outputs are inverted from level L to H.

Therefore, the three-man power of the NAND circuit 34 becomes level L->H, and its output is inverted from level H to L.

At the falling edge, the flip-flop circuit 38 is triggered and the output Q is inverted to level L-H.

This level H output drives an external load via an amplifier or the like (not shown).

When one minute has elapsed, the count of the counter 5 becomes °“3.
Therefore, a level H is generated at the output terminal 3 of the decoder circuit 10, and a level L is generated at the 2 output terminal of the decoder circuit 10.

Therefore, the output of the NAND circuit 34 is inverted from level L to H, but the output Q of the flip-flop circuit 38 is at level H.
hold.

Next, a case will be explained in which the external load is operated at a constant cycle.

First, a case will be described in which an electric signal is generated with a period of W minutes.

The contact pieces 43ay44a of the time setting device 3.44 are connected to the open terminals 43ht44n, and the output thereof is always maintained at level H.

Therefore, assume that the contact piece 42a of the time setting device U is connected to, for example, the 2-minute terminal 42d.

In this state, the two-man power of the NAND circuit 34 is always maintained at level H, and the output level of the NAND circuits 3 and 4 is determined depending on the output level of the time setting device 1.

If the counter 5 is not counting 2°, the output level of the time setting device U is high, and therefore the NAND circuit 3 is
The output of No. 4 is at level H.

When the counter 5 counts "°2°", the terminal 42d changes from level L to H, and the input of the linand circuit 34 changes to level H.

Its output therefore inverts to level H-L, triggering flip-flop circuit 38, which inverts output Q to level L-H to provide a drive electrical signal to the external load.

When 1 minute passes and 3 minutes pass, terminal 42d goes to level H4L.
Therefore, the output of the NAND circuit 34 is inverted to level L-H, but the flip-flop circuit 38 is not triggered and the output Q
is held at level H.

When 9 minutes have passed, 3 minutes have passed, and 3 minutes have passed, the output of the time setting device U becomes level H, and the three-man power of the NAND circuit 34 becomes level H, so its output becomes level L, and the flip-flop circuit 38 is triggered. The output Q is inverted from level H to level L.

In this way, a drive signal is sent to the external load for w minutes.

When 0 minutes have passed, the output Q of the flip-flop circuit 38 is again inverted to the level L-H and a drive signal is supplied to the external load.

Therefore, electrical signals are generated at intervals of w minutes.

Also, a case will be explained in which electric signals are generated at one hour intervals.

The contact pieces 42aw44a of the time setting devices 42, 44 are connected to the open terminals 421.44n, and the output thereof is always maintained at level H.

Therefore, assume that the contact piece 43a of the time setting device 43 is connected to the terminal 43c for 0 minutes, for example.

In this state, the two-man power of the NAND circuit 34 always maintains level H.

When the counter "1" is not counting, the output of the time setting device 43 is at the L level, and therefore the output of the NAND circuit 34 is at the H level.

When the counter 6 counts "1°", the level of the terminal 43c changes from L to H, and the input of the Rinand circuit 34 changes to the H level.

Therefore, its output is inverted from level H to L, triggering the flip-flop circuit 38, and changing the output Q to level L-+H.
The signal is inverted and the drive electrical signal is supplied to the external load.

When w minutes have elapsed and it reaches 209, the terminal 43c goes to level H4.
Although the output of the NAND circuit 34 is inverted to level L-H, the flip-flop circuit 38 is not triggered and the output Q is held at level H.

After five more cycles have passed, the output of the output terminal 43c of 2@ becomes level H, the three-man power of the NAND circuit 34 becomes level H1, so its output becomes level L, the flip-flop circuit 38 is triggered, and its output Q becomes level H. →Flip to L.

In this way, a drive signal is sent to the external load for one hour.

After another hour has elapsed, the output of the flip-flop circuit 38 is again inverted from the level L to the level H, and a drive signal is supplied to the external load.

If the time setting devices 42, 43, and 44 are held in this state, the external load will be driven in one hour cycles.

Further, in the same manner as described above, in order to drive an external load at a cycle of 123G, the contact piece 42aw of the time setting device 42.43 is
43a to the open terminal 42], 43h, and connect the contact piece 44a of the time setting device (() to an appropriate terminal other than the open terminal 44n.

Next, the time reporting operation at the set time will be explained.

First, connect the contact piece 41a of the switch 41 to the contact point 41b,
Prepare for the time report.

The set time is now 1:12 minutes and ω seconds.

Therefore, connect the contact piece 42a of the time setting device ■ to the terminal 42 of the
d, the contact piece 43a of the time setting device 43 is connected to the 1'' terminal 43C, and the contact piece 44a of the time setting device 44 is connected to the 1'' terminal 44c.

At the same time, the three-man power of the NAND circuit 34 becomes level 11, and its output is inverted to level HL.

Therefore, the input of the NOR circuit 31 is inverted to the level H-L, and its gate is opened.

The following time signal has arrived at the NOR circuit 31.

That is, the 2KHz signal shown in Figure 2A is extracted from the output terminal 2a of the divider 2 and supplied to the input terminal 28a of the NOR circuit 28, and the output of the frequency divider 2 is supplied to the other terminal 28b of the NOR circuit 28. A certain 1 second signal of FIG. 2B is provided.

Only when the level of this 1 second signal is L, the 2nd C
A signal of <2 KHz is generated as shown in the figure.

On the other hand, the IKHz taken out from the output terminal 2b of the needle frequency device 2
The signal is supplied to the input terminal 29a of the NOR circuit 29, and the output of the frequency divider 2 is inverted by the inverter circuit 35 and supplied to the input terminal 29b of the NOR circuit 29.

Therefore, since the level H shown in FIG. 2B acts as a level L in the NOR circuit 29, the output terminal of the NOR circuit 29 is
The IKHz signal in diagram E is generated at 0, grain intervals.

Therefore, the input terminal 33a of the NAND circuit 33 has a second F
As shown in the figure <0. The intergranular area is 2KH2% and 0. IKHz between grains
signals are supplied alternately.

An input terminal 33b of the NAND circuit 33 is supplied with a river sand cycle signal shown in FIG. 2G, which is the output of the counter 3.

Therefore, when the pulse g of level H shown in FIG. 2G arrives, a signal 1 shown in FIG. 2H is generated at the output terminal of the NAND circuit 33 and is supplied to the input of the NOR circuit 31.

Now, the input of the NOR circuit 31 is supplied with the level L pulse generated at the set time as described above, and the gate of the NOR circuit 31 is opened, so that the signal shown in FIG. O0 Kuwama is 2KHz,
Further, for 0.5 seconds, an IKHz signal tone is generated alternately for 5 seconds at a 1-second period.

After that, for 5 seconds, the NAND circuit 3
3 input terminal 33b becomes level L, and NAND circuit 33
No time signal is generated at the output of speaker 4.
No signal tone is generated from 0.

In this way, a time signal is generated from the speaker 40 at intervals of 5 seconds, and when 1 minute elapses at 1:13, the decoder circuit 1
The level of "2" of 0 becomes L.

Therefore, since the output of the NAND circuit 34 becomes level H, the input of the NOR circuit 31 also becomes level H, and the NAND circuit 31
The gate is closed and the time signal from the speaker 40 stops.

Next, a fast-forward operation for manually adjusting the time will be explained.

First, the contact piece 37a of the fast-forward switch 11 is connected to the contact point 37c, and the 1-second signal output from the frequency divider 2 is supplied to the NOR circuit 32.

The river sand cycle signal of the counter 4 is supplied to the other input of the NOR circuit 32.

Since this signal is shaped into an impulse shape, all 1 second signals are supplied to the counter 5.

Therefore, the count contents of the counter 5 are sequentially incremented every second, and the count is fast-forwarded.

Next, the reset operation will be explained.

By connecting the contact piece 36a of the reset start switch 36 to the reset side contact 36b, the contents of the frequency divider 2 and counters 3, 4, . . . , 7 are reset.

In this embodiment, a clock with a 1 full period display was explained, but 1
It is also possible to replace the binary counter 7 with a 2-Usuka counter and create a clock with 24I3 Terama display.

When using a 24-hour display, for example, if you drive an external load at a specific time every day, you can simply set the time setting devices 42, 43, and 44 to that specific time, and there is no need to reset it as in the 12B Terama display. do not have.

Further, the counters 3, 4, . . . , 7 are not limited to those in this embodiment, and if necessary, for example, a counter for 1 COfU may be provided to display up to that digit.

Furthermore, in this embodiment, the counters 3, 4, . . . , 7 that generate count outputs for each time unit are collectively referred to as a clock device due to the binary progression, but the decoder circuits 8, 9, . When called a timekeeping device, the counters 3, 4...7 and the decoder circuits 8, 9...12 constitute a timekeeping device.

Therefore, in that case, the display operating device includes decoder circuits 8, 9.
...12 is not included.

The display operating device is a general term for devices that are composed of a circuit that converts the output of a timekeeping device into a driving output of a time display device.

In this embodiment, the time setting devices 42, 43, and 44 have been explained to be used only for setting minutes, w points, and hours, but they may be increased or decreased as necessary.

For example, it may be provided at the second position.

In this embodiment, a flip-flop circuit 38 is used as an example of an external load driving device to supply an electrical signal to the external load. The output signal may be used via an amplifier circuit.

In this case, for example, the time setting devices 43 and 44 are connected to the open terminal 4.
3h*44n, and the time setting device 42 is connected to an appropriate terminal other than the open terminal, a pulse with a pulse width of 1 minute and a repetition period of 10 minutes, that is, a pulse with a duty of 1/10, can be obtained.

Further, in this embodiment, the speaker 40 is provided as the load of the time signal device, but depending on the application, an optical display element such as a light emitting diode may be connected instead of the speaker 40.

In this case, since the time signal is not required, the NOR circuit 2B
, 29, 30, 31, the NAND circuit 33 and the inverter circuit 33 are unnecessary.

The output of the NAND circuit 34 may be directly supplied to the transistor 39 constituting the time signal device via an inverter circuit or the like.

Furthermore, the circuits consisting of NOR circuits, NAND circuits, inverter circuits, etc. used in this example can express the same logical operation with a circuit configuration different from that of this example, so the above circuits can have the same functions. Any logic gate circuit may be used as long as it has the following logic gate circuit.

Although circuit components are not particularly shown in this embodiment, if a MOS transistor is used, for example, the power consumption is extremely low, which is advantageous for a watch.

In particular, in addition to displaying the time as in the present invention, there is a need to operate a speaker or optical display element to signal the time, or to supply an electrical signal to an external load using the output of a timer, which consumes a large amount of power. There is an extremely strong demand for reducing power consumption, and for this purpose, it is advantageous to use MOS transistors that consume less power.

Furthermore, when a transistor circuit is used for the drive device, for example, if a battery in the timepiece device is used, power consumption increases, so the following configuration may be used.

The output terminal of the NAND circuit 34 is connected to the input terminal of a transistor circuit without a power supply, that is, a transistor circuit whose output is open.

and an external option for supplying power to the transistor circuit only when supplying an electric signal to an external load;
By connecting these, a transistor circuit may be activated to extract an electrical signal.

In this way, the built-in power supply of the clock device is not used, so that the power consumption can be reduced accordingly.

In addition, large output can be obtained by using a large capacity power supply as an external option.

As detailed above, the present invention is an electronic device that divides the output frequency of a crystal oscillator using a frequency divider, measures the time using a timekeeping device, and generates sound at a set time using the audible frequency extracted from the frequency divider. Since the clock device is constructed as a digital clock device, there is no need to provide a special signal source for generating sound, and this is advantageous because the number of terminals can be reduced, especially when the circuits are integrated at a high density.

In addition, since it is fully electronic, it consumes less power.In particular, the more functions a clock device has, the more power it consumes.
For example, the use of low power consumption circuit elements such as MOS transistors reduces power consumption, which is extremely advantageous.

Furthermore, since it is possible to create an extremely compact timepiece with a timekeeping function, it is particularly advantageous for a timekeeping wristwatch.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention, and FIG. 1 is a block diagram thereof, and FIG. 2 is a waveform diagram of essential parts for explaining its operation. 1-2... Time signal generator 3-7...
...Clocking device, 8-22... Time display operating device, 23-27 =... Time display device, 38...
... Drive device, 39-41 ... Time signal device, 42
．． 43.44...Time setting device.

Claims (1)

[Scope of utility model registration request] a crystal oscillator, a frequency divider that divides the output frequency of the crystal oscillator, a timekeeping device that receives output pulses from the frequency divider, a time display device that displays according to the output of the timekeeping device, and the timekeeping device described above. A scheduled time output device that selects the output terminal of each digit of the device with a contact piece to set the scheduled time and generates the output at ', and receives a pulse train from the above-mentioned branching device and generates pulses of audible frequency intermittently. An electronic timepiece device comprising: a logic gate circuit that outputs the scheduled time; a time signal device; and a circuit that supplies the output of the logic gate circuit to the time signal device in response to the output of the scheduled time output device.