JPS5936231B2 - Electronic clock with power outage detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece with a power failure detection device that logically detects a power outage of an AC power source in an electronic timepiece or the like that performs a timekeeping operation based on the frequency of a commercial AC power source.

The frequency of commercial AC power is extremely stable;
For this reason, electronic watches have been considered that perform timekeeping operations based on the frequency of a commercial AC power source.

In this case, if a power outage accident occurs in the AC power supply, the operation of the timing circuit will stop, so a power outage detection circuit is installed to detect the power outage, and the power outage detection signal is used to continue driving the timing circuit using the internal power supply. I have to. Conventional power outage detection methods use, for example, an element that detects the level of AC power supply voltage, and when this voltage level drops below the rated value of the element, it is assumed that a power outage has occurred and outputs a power outage detection signal. I have to. However, detecting analog level changes in the power supply voltage using a detection element in this manner is not only unsuitable for LSI implementation, but also increases costs. The present invention has been made in view of the above points, and detects the occurrence of a power outage quickly and reliably by comparing and detecting clock pulses generated by an internal power source and clock pulses generated based on the frequency of a commercial AC power source. The purpose of the present invention is to provide a clock with a power failure detection device that can detect power failures.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 11 denotes a commercial AC power source with a frequency of, for example, 50H2, and the output voltage of this commercial AC power source 11 is rectified by a diode 12, and then passed through a noise filter 16, which is constituted by, for example, resistors 13, 14, and a capacitor 15. The signal is sent to the waveform shaping circuit 17 via the waveform shaping circuit 17, where the waveform is shaped into a rectangular wave. The output of this waveform shaping circuit 17 is sent to a one-shot generating circuit 18. This one-shot generation circuit 18 is configured to read an input using, for example, a word pulse φe, output a signal using a clock pulse φ2, delay flip-flop circuits 19 and 20, and output from the flip-flop circuit 19. It consists of an AND circuit 22 to which the output of the flip-flop circuit 20 is added via an inverter 21. The pulse signal output from the AND circuit 22 is then sent as a +1 signal to the adder circuit 24 in the timer section 23. The adder circuit 24 is connected in a ring shape to a shift register 25 operated by short-cycle clock pulses φ1φ2, and a +1 signal output from the AND circuit 22 is applied to the stored contents of a specific digit of the shift register 25. Add.
Further, a carry control circuit 26 is connected to the adder circuit 24, and the carry control circuit 26 controls the shift register 2.
The contents of 5 are carry-controlled according to the count value. Further, the output of the AND circuit 22 is applied to one input terminal of an AND circuit 28 in the power failure detection section 27. The word pulse φ2 outputted from the clock timing signal generation circuit 29 is applied to the other input terminal of the AND circuit 28. The above clock timing signal generation circuit 2
9 is the clock pulse φ1. φ2, word pulses φE, φF, φG having timings as shown in FIG. 2 and sufficiently shorter periods than the commercial power frequency, and pulse signals Pa of 30 Hz, for example, having a sufficiently longer period than the commercial power frequency. The word pulse φf and the 30Hz pulse signal P output from the clock timing signal generation circuit 29
a is applied to different input terminals of an AND circuit 30, and the output of this AND circuit 30 is applied to a reset terminal R of a flip-flop circuit 31. Further, the output of the AND circuit 28 is applied to the set terminal S of the flip-flop circuit 31 and the set terminal S of the flip-flop circuit 32.
added to. And the flip-flop circuit 31 described in ±
The Q side output of the clock timing signal generation circuit 29
The output of the AND circuit 33 is applied to different input terminals of the AND circuit 33 along with the pulse signal Pa of the word pulse φGl3OHz outputted from the flip-flop circuit 3.
It is applied to the reset terminal R of No.2. The signal output from the O-side output terminal of this flip-flop circuit 32 becomes a power failure detection signal. In addition, each of the above circuits is connected to the AC power supply 11.
The operating voltage is supplied from an internal power supply unrelated to the
The AC power supply 11 is used only to obtain a reference pulse signal to the timer section 23. Next, the operation of the present invention configured as described above will be explained.

First, the normal operation when the AC power supply 11 is normally supplied will be explained with reference to the timing chart shown in FIG. The output voltage of the AC power supply 11 is
After being rectified, the signal is sent to a waveform shaping circuit 17 where it is waveform-shaped into a rectangular wave signal as shown in FIG. The signal output from this waveform shaping circuit 17 is the word pulse φ
The signal is read into the flip-flop circuit 19 in synchronization with e, and is outputted from the flip-flop circuit 19 in synchronization with the next applied clock pulse φ2. At this point, the output of the flip-flop circuit 20 is 60'', the output of the inverter 21 is 811, and the gate of the AND circuit 22 is open, so the output of the flip-flop circuit 19 is immediately output from the AND circuit 22. The output of the circuit 19 is read into the flip-flop circuit 20 in synchronization with the word pulse φe, and the clock pulse φe
It is output from the flip-flop circuit 20 in synchronization with 2. When the flip-flop circuit 20 outputs a 61° signal, the output of the inverter 21 becomes "01" and closes the gate of the AND circuit 22. In this way, the AND circuit 22 outputs a signal with a frequency of 50Hz as shown in FIG. A reference pulse signal synchronized with the clock pulse φe is output and sent to the timer 23.The timer 23 counts the reference pulse signal output from the AND circuit 22 to obtain time information regarding hours, minutes, seconds, etc. Although not shown, this time information is sent to the display section and displayed digitally.Also, the output signal of the AND circuit 22 is sent to the AND circuit 28.
be sent to open the gate. When the gate of AND circuit 28 is open, word pulse φe applied from clock timing signal generation circuit 29 is output from AND circuit 28 and sets flip-flop circuits 31 and 32. On the other hand, as shown in FIG. 3, the word pulse φf is output from the AND circuit 30 when the 30 Hz pulse signal Pa and the word pulse φf are applied simultaneously, and the flip-flop circuit 31 is reset. In this case, the period of the pulse signal Pa applied to the AND circuit 30 is set to be sufficiently longer than the period of the AC power supply 11, so that when the AND circuit 30 outputs a "1" signal, the flip-flop circuit 31 is always set. state, and its Q side output is "O". Therefore, the gate of the AND circuit 33 is always closed at the time when the word pulse φg is output together with the 30 Hz pulse signal Pa, and the AND circuit 3
The output of the flip-flop circuit 3 is always in the 60" signal state. Therefore, if the AC voltage 11 is normal, the flip-flop circuit 3
2 is never set and no power failure detection signal is output. However, if the AC power supply 11 were to experience a power outage, as shown in FIG.
The reference pulse signal is no longer output.

Therefore, after a power outage occurs, the word pulse φf output from the AND circuit 30 causes the flip-flop circuit 31 to switch to the fourth
After the flip-flop circuit 31 is reset as shown in the figure, the flip-flop circuit 31 is set.
The state in which the signal is output is maintained. Therefore, if the word pulse φg is generated while the next pulse signal Pa is being applied to the AND circuit 33, this card pulse φ
g is output from the AND circuit 33 and resets the flip-flop circuit 32. Therefore, as shown in FIG. 4, a 61'' signal, that is, a power failure detection signal, is output from the Q side output terminal of the flip-flop circuit 32.When this power failure detection signal is output, for example, although not shown, the internal power supply For example, a reference pulse signal from an internal oscillator operated by the clock unit 23 is sent to the clock unit 23, and the circuit is switched so that the clock unit 23 continues to perform the clock operation even after a power outage. Since the power outage is detected by comparing the reference pulse signal generated based on the frequency of the commercial AC power source 11 and the pulse signal generated by the internal power source, the power outage is detected digitally, that is, logically. It is possible to quickly and reliably detect the occurrence of a power outage.Also, since everything is done using logical circuits, it is suitable for LSI implementation and has great effects, such as being low in cost. It should be noted that the present invention can be applied not only to electronic clocks such as table clocks, wall clocks, time recorders, and parent-child clocks, but also to electronic desk calculators with clocks, and that various design changes may be made without departing from the gist of the present invention. Of course.

Therefore, according to the present invention, it is possible to provide a timepiece with a power failure detection device that can logically detect the occurrence of a power failure quickly and reliably with a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2 to 4 are timing charts for explaining the operation of the embodiment. DESCRIPTION OF SYMBOLS 11... Commercial AC power supply, 18... One shot generation circuit, 23... Timing unit, 27...
...Power failure detection section.

Claims (1)

[Claims] 1 means for generating a first pulse signal based on the frequency of an alternating current power supply; a timekeeping circuit that counts this first pulse signal to obtain time information; means for generating a second pulse signal; first storage means set by the second pulse signal and reset by the first pulse signal; a detection means for detecting that the contents of the storage means have not been reset when the next second pulse signal is output; and a reference from an oscillator operated by an internal power supply based on the detection output from the detection means. An electronic timepiece with a power failure detection device, comprising means for supplying pulses to the timepiece circuit.