JPS6311638B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an all-electronic analog display timepiece using a liquid crystal or the like.

For example, in a watch that uses a liquid crystal display to display the time, the second hand and minute hand are the same size and shape, so when the minute hand is fast forwarded when setting the time, the second hand and minute hand become confusing. This makes it difficult to adjust the timing. In particular, when the time setting speed is increased when the temperature is low, the response of the minute hand display cannot follow this speed, causing the problem that the minute hand disappears and the display stops.

Therefore, the present invention provides an all-electronic analog display timepiece that makes it easier to set the time by erasing the second hand display and preventing the minute hand from disappearing when the minute hand is fast forwarded.

An embodiment of the present invention will be described below based on the drawings. In Figure 1, 1 is a crystal oscillator, 2 and 3 are frequency dividers that generate pulses with a period of 1 second, and 4 and 5 are frequency dividers that generate pulses with a period of 1 second.
are a decimal counter and a hexadecimal counter that measure seconds, respectively. 6 and 7 are a decimal counter and a hexadecimal counter that respectively measure the minute digit, and 8 and 9 are a decimal counter and a hexadecimal counter that measure the hour digit, respectively.
It produces an evolved decimal code output. 10
is a hexadecimal counter, 11 is a binary counter, 12 is a timing pulse generation circuit, and from frequency divider 2,
For example, in response to an output pulse of 128 Hz, a timing pulse is generated at terminals p ₁ to _{p 3} for sequentially selecting the second hand, minute hand, and hour hand in this order in a time-sharing manner. Each timing pulse has a frequency of 128 Hz, a duty of 1/3, and a phase shifted by 1/3 period, and these pulses are generated cyclically. 13 to 18 are gate circuits having an AND function, which are controlled by pulses from terminals q ₁ and q ₂ . 19 and 20 are gate circuits having an OR function. 21 and 22 are respectively gate circuits 1
This is a decoder that converts 9 and 20 output codes. The decoder 21 inputs the time measurement outputs of the time measurement circuits 4, 6, and 8 in units of 1 second, 1 minute, and 12 minutes supplied from the gate circuit 19 in a time-division manner, and outputs the time measurement outputs of the time measurement circuits 4, 6, and 8 in units of 1 second, 1 minute, and _{12 minutes, which are supplied from the gate circuit 19 in} a time-division manner. Among them, a selection output is generated from a terminal corresponding to the above-mentioned time measurement output. That is, 1,
When time measurement outputs of 2 to 9 and 0 seconds are input, selection outputs of terminals _e1 to _e10 are generated from output terminals _x0 to _x9 , respectively. A similar operation is performed for minutes and hours. In addition, the decoder 22 inputs the time measurement outputs of 10 seconds, 10 minutes, and 10 o'clock supplied in a time-division manner from the gate circuit 20, and connects the electrode terminals g ₁ to _{g 6} and k ₁ to
k ₆ , which generates a selection output corresponding to the above-mentioned time measurement output. That is, when a time measurement output of 0, 10 to 50 seconds is input, selection outputs of terminals _g1 to _g6 and terminals _k1 to _k6 are generated from output terminals _y0 to _y5 , respectively. A similar operation is performed for minutes and hours. 23 is an output order switching circuit, and the output order of the decoder 21 is switched according to the state of one output of the gate circuit 20. 24 is a segment potential setting circuit that selects a potential to be applied to the segment electrodes, which will be described later, and 25 is a common potential setting circuit that selects a potential to be applied to the common electrode. 2
6 is _a potential setting circuit whose detailed circuit is shown in _{FIG .} is the potential 3V ₀ to make the liquid crystal respond
and 0 are generated alternately, and potentials V0 and 2V0 for holding the liquid crystal in a non-responsive state are alternately generated at the terminal _S1 . In addition, voltage to be supplied to the common electrode is generated from terminals C0 and _C1 at a cycle of 1/64 seconds, and potentials 0 and 3V ₀ are alternately generated at terminal _C0 , and potential is generated at terminal _C1 . 2V ₀ and V ₀ occur alternately. FIG. 8 shows the voltage applied to the liquid crystal due to this potential. 27 and 28 are flip-flop circuits, 29 is a pulse control circuit to be described later, and 3
0 to 32 are gate circuits, and 33 is an inverter. 34 is a timing pulse generator (for example, JP-A-53
-131874), and pulses are generated according to the manual operation speed. 35 is a timing lock switch, and during timing, this switch 35 resets the frequency division stages lower than the frequency division stage that generates the 64 Hz pulse in frequency divider 2, and also resets frequency dividers 4 and 5. . 36 is a resistance.

FIGS. 2 and 3 show electrode patterns of a liquid crystal display device that displays hands.

In FIG. 2, numeral 37 indicates the arrangement of 60 segment electrodes 37a...37a, and the 10 segment electrodes 37a...37a are connected to the terminals _e1 to 37a of the segment potential setting circuit 24 as shown in the figure. It is connected to e ₁₀ . Other segment electrodes have the following connection relationships. Note that the order of the segment electrodes referred to below is counted clockwise, with the segment electrode 37a connected to the terminal _e1 being the first. The 10th segment electrode 37a is connected to the 11th segment electrode 37a, the 9th to the 12th, the 1st to the 20th, and then the 11th to the 11th.
The 20th becomes the 21st, the 19th becomes the 22nd, etc.
The 11th is commonly connected to the 30th. Below, segment electrodes up to the 60th are connected in the same relationship as above.

FIG. 3 shows a common electrode pattern 38 , in which six common electrodes 38b and 38a are formed on the outside and inside.

Note that the dividing groove 38c of the common electrodes 38a, 38b...
...38c is between the 10th and 11th segment electrodes, between the 20th and 21st segment electrodes, between the 30th and 31st segment electrodes, and between the 30th and 31st segment electrodes in the clockwise direction.
Between the 40th and 41st segment electrodes, the 50th and
Between the 51st segment electrode and the 60th, 1
It is configured to be located between the segment electrodes.

Note that a liquid crystal display device is composed of a collection of display parts with a liquid crystal interposed between segment electrodes and a common electrode, but the configuration can be easily implemented by the person concerned, and is also described in this book. Since the invention is not characterized by such a configuration itself, the description thereof will be omitted.

FIG. 4 is a detailed circuit diagram of the output priority switching circuit 23 and the segment potential setting circuit 24.
53 is a gate circuit, 54 to 63 are analog switches, and 64 to 68 are inverters.

FIG. 5 is a detailed circuit diagram of the potential setting circuit 26, in which 69 to 76 are analog switches and 77 is an inverter.

FIG. 6 is a detailed circuit diagram of the common potential setting circuit 25, in which 78-83 are gate circuits, 84-93 are analog switches, and 94-98 are inverters.

FIG. 7 is a detailed circuit diagram of the pulse control circuit 29, in which 99 is an inverter and 100 to 102 are gate circuits. Inverter 99, gate circuit 100
constitutes a first control circuit, and gate circuit 1
01 and 102 constitute a second control circuit.

In the above configuration, the state of the potentials to be applied to the segment electrodes and the common electrode will be explained. The potentials are 0, V ₀ , 2V ₀ and 3V ₀ , and for the purpose of explanation, the display device in this example is assumed to be off when the voltage is below |V0|, and to be lit when the voltage is above |3V0|. In FIG. 5, terminals l ₁ and l ₄ are 0, terminals l ₂ ,
A voltage of _v0 is applied to _l7 , a voltage of _2V0 is applied to terminals _l3 and _l6 , and a voltage of _3V0 is applied to terminals _l0 and _l5 . A pulse train is periodically generated at the output Q of the flip-flop circuit 27 by a pulse from the terminal _p1 of the timing pulse generating circuit 12 shown in FIG. As a result, the potentials 0 and 3V ₀ are applied to the terminal S ₀ shown in FIG. 5, the potentials V ₀ and 2V ₀ are applied to the terminal S ₁ ,
Voltage 0 and 3V ₀ on terminal C ₀ , potential 2V0 on terminal C1
and V0 occur alternately. Figure 8 summarizes this relationship. In the same diagram, each terminal S ₀ ,
V _{s and} V _c shown corresponding to S ₁ and C ₀ and C ₁ are applied to each terminal in order from the left every time a pulse is generated at terminal p ₁ .
The potentials generated at S ₀ , S ₁ and C ₀ , C ₁ are shown.
The remainder of the diagram shows the difference in potential simultaneously occurring between each terminal S ₀ , S ₁ and terminal C ₀ , C ₁ , that is, the voltage V _sc . As is clear from the figure, when a potential is applied to the terminals S ₀ and C ₀ , the corresponding display section lights up.

Therefore, the case of normal time display will be explained. In this display state, it is assumed that the switch 35 in FIG. 1 is open and the flip-flop circuit 28 is reset. As is clear from the seventh diagram, the output Q of the flip-flop circuit 28 causes the terminal q ₁ to be connected to the terminal p ₁ and the terminal q ₂ to be connected to the terminal p 1 .
Each pulse train of p ₂ is applied. As an example,
The pointer display when the counters 4 to 9 shown in the first figure measure 10:05:00 will be explained. In this timekeeping state, counter 4 is "0" and counter 5 is "0".
is "0", counter 6 is "5", counter 7 is "0", counter 8 is "0", counter 9 is "5"
are being counted. Therefore, if we pay attention only to the terminal _p1 of the timing pulse generation circuit 12 shown in FIG.
The second digit gate circuits 13 and 16 are opened by the generated pulse train, and the seconds data of the counter 4 is input to the gate circuit 19, and the seconds data of the counter 5 is input to the gate circuit 20. Therefore, "0" is produced at the terminals 2 ⁰ to 2 ³ of the gate circuit 19, and "0" is produced at the terminals 2 ⁰ to 2 ² of the gate circuit 20. Therefore, a "1" is generated at the terminal, a "0" is generated at the terminal h, and a "1" is generated at the terminal _x0 of the decoder 21.
Therefore, referring to FIG. 4, gate circuits 39, 4
Since the output of 9 becomes "1", the potential generated at the terminal _S0 is generated at the terminal _e1 . For other terminals e ₂ to e ₁₀ , analog switches 57, 59, 61, 63
turns on, resulting in a potential at terminal _S1 .

Next, regarding the decoder 22 shown in the first diagram, since "1" is generated at the terminal y0, the potential generated at the terminal _C0 is generated at the terminal _k1 shown in the sixth diagram. In addition, “1” is applied to the terminal _p1 of the timing pulse generation circuit 12.
While this is occurring, the terminal _p3 maintains the "0" state, so the terminal ₃ is "1" and therefore the gate circuits 78-83 are open. Therefore, the analog switch 84 is turned on, and the potential occurring at the terminal _C0 is generated at the terminal _g1 . Other terminals k ₂ to k ₆ ,
The potential occurring at terminal _C1 is generated between _g2 and _g6 . As a result of the above, as is clear from the potential and voltage chart shown in FIG. 8, the display section corresponding to the segment electrode S shown in FIG. 2, that is, the seconds hand display section is lit.

Next, the terminal p ₂ of the timing pulse generation circuit 12
When paying attention to , the pulse train generated from the terminal opens the gate circuits 14 and 17 and passes through the data "5" and "0" of the counters 6 and 7. Therefore, “1” is generated at the terminal x ₅ of the decoder 21 and “1” is generated at the terminal y ₀ of the decoder 20, or “1” and h is “0”.
become.

As a result, the output of the gate circuit 51 shown in FIG. 4 becomes "1", the analog switch 58 is turned on, and the potential generated at the terminal _S0 is generated at the terminal _e6 . The potential occurring at the terminal _S1 is generated at the other terminals e1 _{to e5 and e7} to _e10 .

Also, according to FIG. 6, the potential that occurs at terminal C ₀ is generated at terminals g ₁ and k ₁ , and the potential that occurs at terminal C 0 is generated at terminals g ₁ and k 1 , and the potential that occurs at terminal C 0 is generated at terminals g ₁ and k ₁ .
The potential that appears at terminal _C1 is generated at _k6 . Therefore, as is clear from the diagram shown in FIG. 8, the segment electrode M (see FIG. 2) corresponding to the terminal e ₆ and the terminal g ₁ ,
The display section formed by the common electrode corresponding to _k1 lights up.

Focusing on the terminal _p3 of the timing pulse generation circuit 12, the pulse train generated at the terminal opens the gate circuits 15 and 18, and passes through the gate circuits 15 and 18 to the counters 8 and 18.
Pass the output of 9. As a result, the potential generated at the terminal S ₀ is generated at the terminal e ₁₀ of the segment potential setting circuit 24, and the potential generated at the terminal C ₀ is generated at the terminal k ₆ of the common potential setting circuit 25. Other terminal k ₁
~ _k5 generates the potential that appears at terminal _C1 . Note that when a pulse is generated at the terminal p3, the outputs of the gate circuits 78 to 83 shown in FIG. 6 become "0", so that the potential occurring at the terminal _C1 is generated at the terminals _g1 to _g6 .

Therefore, the display section is illuminated when it is constituted by the segment electrode H (see FIG. 2) corresponding to the terminal e ₁₀ and the common electrode corresponding to the terminal k ₆ .

As described above, the segment electrode H shown in the second diagram,
The display parts corresponding to M and S are lit, and it is 10:05:00.
Seconds are displayed. In this way, in normal times, when one time-division period is t, the time-division drive time of the second hand, minute hand, and hour hand is t/3, respectively.

Next, the timing operation will be explained. When the switch 35 shown in the first figure is closed, the frequency divider 2 and second counters 4 and 5 are reset, the contents of the counters become "0", and the second hand displays 00 seconds. Furthermore, the gate circuit 30 is opened, allowing the timing pulse to pass through. Therefore, when a timing pulse is generated manually from the timing pulse generator 34, the contents of the counters 6 to 9 change according to the input pulse, and the minute hand display rotates in accordance with the rate at which the timing pulse is generated. Counter 11 by timing pulse
is reset, and the flip-flop circuit 28 is also set. Therefore, the terminal q ₀ in Fig. 7 becomes "1", the terminal q ₁ becomes "0", the terminal q ₂ becomes the terminal p ₁ ,
A pulse occurs that occurs at p ₂ . The seconds gate circuits 13, 16 thus remain closed, the minutes gate circuits 14, 17 are opened during seconds and minutes digit selection, and the hours gate circuits 15, 18 are applied to terminal _p3. Opened by a pulse. Second gate circuit 1
3 and 16 are closed, the second display disappears, and the person setting the time can set the desired time while looking at the minute hand display and the hour hand display without being confused with the second display. In addition, the minute gate circuits 14 and 17 are open for twice as long as in the case of a normal time display, that is, the time-division driving time of the minute hand display is 2t/3, which is twice the normal time. Therefore, the time-division drive time of the liquid crystal in the minute hand display section is twice as long as normal, and the response speed of the liquid crystal becomes faster. Therefore, even if the frequency of the timing pulse becomes relatively high, the display of the minute hand does not disappear, and the timing can be set quickly.

When the timing is completed and approximately 1 to 2 seconds have passed since the generation of timing pulses has stopped, an output is generated from the counter 11, and the flip-flop circuit 28 is reset.
The seconds display will appear. At this time, seconds counters 4 and 5
Since it is in the reset state, the second hand is pointing to 00 seconds. So, for example, if the switch 3 is turned on at the same time as the time signal,
5 is opened to release the reset of frequency divider 2 and counters 4 and 5, each counter 4 to 9 starts measuring time, and normal timekeeping is performed.

In the above embodiment, the seconds display is erased by closing the seconds gate circuits 13 and 16 during time adjustment, but the present invention is not limited to this. For example, during timing, the _segment potential setting circuit 24
The potential occurring at the terminal _S1 may be generated from each of the terminals _e1 to _e10 .

Further, in the above embodiment, the second hand is erased upon generation of the timing pulse, but the present invention is not limited to this, and the second hand display may be erased by closing the timing lock switch 35. In this case, the frequency divider 3, counter 11, flip-flop circuit 28 and gate circuit 32 are not necessary, and the output of the timing lock switch 35 may be connected to the terminal _q0 .

As described above, according to the present invention, since the second hand display is erased when setting the time, confusion between the minute hand display and the second hand display is eliminated, making it easier to set the time. Moreover, since the time-division drive time of the second hand display is added to the time-division drive time of the minute hand display,
The response speed of the liquid crystal becomes faster, and the minute hand display does not disappear even during fast forwarding, making it easier to set the time.

[Brief explanation of the drawing]

Fig. 1 is an electrical circuit diagram of an embodiment of the present invention;
The figure is a plan view of the segment electrode pattern of the display device, FIG. 3 is a plan view of the common electrode pattern of the display device, and FIGS. 4 to 6 are partial detailed circuit diagrams of FIG. 1.
Figure 7 is a detailed circuit diagram of the main parts of Figure 1, and Figure 8 is a detailed circuit diagram of the main parts of Figure 1.
3 is a potential and voltage chart for explaining the operation of the circuit shown in the figure. 4-9... Counter, 12... Timing pulse generation circuit, 13-18... Gate circuit, 28...
...Flip-flop circuit, 29... Pulse control circuit, 30-32... Gate circuit, 34... Timing pulse generation circuit, 35... Timing lock switch, 9
9...Inverter, 100-102... Gate circuit.

Claims (1)

[Claims] 1. A clock circuit that measures the time, a display device consisting of a liquid crystal that displays time hands, and a drive circuit that receives the output of the clock circuit and drives the display device in a time-divisional manner to display an hour hand, a minute hand, and a second hand. and a timing device for timing the contents of the timing circuit;
a first control circuit that erases the second hand display on the display device when setting the time; and a second control circuit that adds the time-division drive time of the second hand display to the time-division drive time of the minute hand display when the time is set. All-electronic analog display clock.