JPS6349748Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a display device for an electronic watch.

Conventional analog electronic timepiece display devices are broadly classified into those using a mechanical hand-type display and those using an optical display in place of the hand-type display. The majority of the latter display devices have been those in which light-emitting elements such as light-emitting diodes are arranged in a circular shape, and display the elapsed time by cumulatively displaying the light-emitting elements or by sequentially changing the lighting state. In a watch that has such a display state, when the display section is provided to display AM and PM, the number of terminals of the drive circuit generally increases. In addition, the display space is limited, especially in small watches, which is a constraint.

SUMMARY OF THE INVENTION Therefore, the present invention provides a display device for an electronic timepiece that changes the display mode when the hands are indicating a predetermined time zone in an analog watch that displays the time using an optical hand display. be.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a crystal oscillator, 2 is a frequency divider, and these constitute a reference pulse generation circuit. 3 and 4 are decimal and hexadecimal counters that measure the seconds digit, respectively, 5 and 6 are decimal and hex counters that measure the minute digit, respectively, and 7 and 8 are the hour digits, respectively. to time
They are a decimal counter and a hexadecimal counter. Each of the above counters produces a binary coded decimal code output. 9
is a hexadecimal counter. The above counter constitutes a timekeeping circuit. Reference numeral 10 denotes a timing pulse generation circuit, which sequentially generates pulses at terminals P ₁ to _{P 3} in conjunction with the generation of output pulses from the frequency divider 2. 11~
Reference numeral 16 constitutes a selection circuit and is a gate circuit having an AND function, which is controlled by pulses sequentially generated at terminals _P1 to _P3 . 17 and 18 are gate circuits having an OR function. Decoders 19 and 20 convert the output codes of the gate circuits 17 and 18, respectively. Reference numeral 21 denotes an output order switching circuit, which switches the output order of the decoder 19 in accordance with one output state of the gate circuit 18. 22 is a segment potential setting circuit that selects the potential to be applied to the segment electrodes, which will be described in detail later, and 23 is a common potential setting circuit that selects the potential to be applied to the common electrode. From the above gate circuits 17 and 18 to the common potential setting circuit 2
The circuits up to 3 constitute a voltage supply circuit. 24 is a flip-flop circuit, 25 is a morning and afternoon detection circuit, and when the logic value of terminal q is "1" (hereinafter simply referred to as "1"), the afternoon logic value is "0".
(hereinafter simply referred to as "0") is defined as morning. 26 is a potential setting circuit, and each terminal S0, S
1, C0, C1 have potentials 0, v0, 2v0 and 3
A predetermined potential of v ₀ is generated periodically. The flip-flop circuit 24 and the potential setting circuit 26 constitute a pulse setting circuit. 27 is an inverter. 2
8 and 29 are switching circuits made of semiconductors, 3
0 is an inverter, and 31 is a gate circuit. The inverter 27, switching circuits 28, 29, and gate circuit 31 constitute a blinking circuit.

FIGS. 2 and 3 show electrode patterns of a liquid crystal display device that displays hands.

In FIG. 2, numeral 32 indicates the arrangement of segment electrodes with 60 electrodes, and segment electrodes 32a...32a with 10 electrodes are the terminals of the extraction electrodes 33 to be connected to the segment potential setting circuit 22 as shown in the figure.
e ₁ to _{e 10} are connected. Other segment electrodes have the connection relationships shown below. Note that the order of the segment electrodes is counted clockwise, with the segment electrode 33a connected to the terminal _e1 being the first. The 10th segment electrode 33a is the 11th segment electrode 33a, and the 9th segment electrode 33a is the 11th segment electrode 33a.
The 12th...the 1st becomes the 20th, the 20th becomes the 21st, the 19th becomes the 22nd...the 11th becomes 30...
It is connected in common with the th. Below, segment electrodes up to the 60th are connected in the same relationship as above.

FIG. 3 shows a common electrode pattern 34, which includes common electrodes 34a and 34b divided into six parts on the outside and inside.

Note that each dividing groove 34 of the common electrodes 34a and 34b
c...34c is between the 10th and 11th segment electrodes, between the 20th and 21st segment electrodes, between the 30th and 31st segment electrodes, and between the 40th and 41st segment electrodes in the clockwise direction. between the th segment electrodes,
Between the 50th and 51st segment electrodes and between the 50th and 51st segment electrodes.
It is configured so that it can be located between the 60th and 1st segment electrodes.

Note that a liquid crystal display device is constituted by an assembly of display parts with liquid crystal interposed between segment electrodes and a common electrode, but the configuration can be easily implemented by a person skilled in the art, and The present invention is not characterized by such a configuration, so a description thereof will be omitted.

FIG. 4 is a detailed circuit diagram of the output priority switching circuit 21 and the segment potential setting circuit 22.
49 is a gate circuit, 50 to 59 are the same switching circuits as shown in the first diagram, and 60 to 64 are inverters.

FIG. 5 is a detailed circuit diagram of the potential setting circuit 26, in which 65 to 72 are switching circuits, and 73 is an inverter.

FIG. 6 is a detailed circuit diagram of the common potential setting circuit 23, in which 74 to 79 are gate circuits, 80 to 89 are the same switching circuits as shown in the first figure, and 90 to 94 are inverters.

In the above configuration, the state of the potentials to be applied to the segment electrodes and the common electrode will be explained. The potentials are assumed to be 0, v ₀ 2v ₀ and 3v ₀ , and the liquid crystal display device in this example is assumed to be off when the voltage is below |V ₀ |, and to be lit when the voltage is above 3|v0|. In Figure 5, 0 is applied to terminals l ₁ and l ₄ , and 0 is applied to terminals l ₂ and l _7.
A potential of 2v ₀ is applied to the terminals l ₃ and l ₆ , and a potential of 3v ₀ is applied to the terminals l ₀ and l ₅ . When "1" is periodically generated at the terminal _P1 of the timing pulse generation circuit 10 shown in FIG.
“0” occurs alternately. As a result _, potentials ₀ and 3v ₀ are alternately applied to _{the terminal} S _{0 shown in FIG .} occurs in Figure 7 summarizes this relationship. In the same chart, the types of potentials V _{s and} V _c shown corresponding to each terminal S ₀ , S ₁ and C ₀ , C ₁ are applied to each terminal S ₀ in order from the left every time a pulse is generated at terminal P ₁ . , S ₁ and C ₀ , C ₁ are shown. The remainder of the diagram shows the difference in potential that occurs simultaneously at each terminal S ₀ , S ₁ and terminal C ₀ , C ₁ ,
That is, the potential Vs-c is shown. As is clear from the figure, when a potential is applied to the terminals S ₀ and C ₀ , the corresponding display section is lit.

As an example, if the counters 3 to 8 shown in the first figure are
The pointer display when the time is 10:05 will be explained. In this timekeeping state, the counter 3 is
"5", counter 4 is "0", counter 5 is "0",
The counter 6 counts "0", the counter 7 counts "0", and the counter 8 counts "5". Therefore, each time a pulse is periodically generated at the terminal _P1 of the timing pulse generating circuit 10 shown in FIG. Then, the second data of the counter 4 is input to the gate circuit 18. Therefore, "1" is produced at the terminals 2 ⁰ and 2 ² of the gate circuit 17, and "0" is produced at the terminals 2 ⁰ -2 ² of the gate circuit 18. Therefore, “1” is placed at terminal h,
“0” to terminal h, “1” to terminal _x5 of decoder 19
occurs. Therefore, referring to FIG. 4, since the outputs of the gate circuits 39 and 47 become "1", the terminal u
A potential occurs at terminal e ₆ .

Here, the following pulse signals are applied to the terminal u. In FIG. 1, since afternoon timekeeping is being carried out, the terminal q of the detection circuit 25 is at "1", and since a pulse is being generated at the terminal _P1 , the gate circuit 31 is opened. Therefore,
Pulse signal generated at terminal _P4 of frequency divider 2,
For example, a _2H2 pulse signal passes through the gate circuit 31 and alternately switches the switching circuits 28 and 29. Therefore, the potential that occurs at the terminals S ₀ and S ₁ is periodically generated at the terminal u, and the potential is generated at the terminal e ₆ . Note that the period of the signal pulse generated at the terminal _P4 is determined as appropriate as necessary. Now, regarding the other terminals e ₁ to e ₅ and e ₁ to e ₁₀ , the switching circuits 51...53,...57, 59
turns on, resulting in a potential at terminal _S1 .

Next, regarding the decoder 20, since "1" occurs at the terminal y ₀ , the terminal C ₀ is output from the terminal k ₁ shown in the sixth diagram.
A potential is generated. Also, since the terminal _P3 of the timing pulse generation circuit 10 is "0", the terminal
_P3 is "1" and gate circuits 74-79 are open. Therefore, the switching circuit 80
turns on, and the potential occurring at terminal C ₀ is generated at terminal q ₁ . Other terminals _k2 to _k6 , _g2 to _g6 have terminals
The potential occurring at C ₁ is generated. As a result, the display portion is lit when the potential generated at the terminal S ₀ is applied to the terminal e ₆ and is turned off when the potential generated at the terminal S ₁ is applied. Therefore, the seconds hand display section blinks.

Next, the terminal of the timing pulse generation circuit 10
When a pulse is periodically generated on P ₂ , gate circuits 12 and 15 are opened, and each data "0" of counters 5 and 6 passes through them. Therefore, “1” is generated at the terminal x ₀ of the decoder 19, “1” is generated at the terminal y ₀ of the decoder 20, and h is “1” and h is “0”.
hold.

Therefore, the output of the gate circuit 45 in FIG. 4 becomes "1", the switching circuit 50 is turned on, and the potential present at the terminal u is produced at the terminal _e1 . In the case of minute display, since the terminal _P1 is "0", the potential generated at the terminal _S0 is generated at the terminal _e1 . The potential occurring at the terminal S1 is generated at the other terminals e2 to e10.

Also, from FIG. 6, the potential that occurs at terminal C ₀ is generated at terminals g ₁ and k ₁ , and the potential that occurs at terminal C 0 is generated at terminals g 1 and k 1 , and the potential at other terminals g ₂ to g ₆ and k ₂ to
The potential that appears at terminal _C1 is generated at _k6 . Accordingly, the display portions corresponding to the terminal e ₁ and the terminals g ₁ and k ₁ are lit according to the chart shown in FIG.

The gate circuit 1 is activated by the pulses periodically generated at the terminal _P3 of the timing pulse generation circuit 10.
3 and 16 are opened, and the outputs of counters 7 and 8 pass through. As a result, the segment potential setting circuit 22
The potential that occurs at terminal S ₀ is generated at terminal e _{10 of} . The potential generated at the terminal C0 is generated at the terminal _k6 of the common potential setting circuit 23, and the potential generated at the terminal _C0 is generated at the other terminals _k1 to _{k5 .}
A potential is generated. Note that when a pulse occurs at the terminal _P3 , the gate circuits 74 to 74 shown in FIG.
Since the output of 79 becomes "0", the potential occurring at terminal _C1 is generated in all terminals _g1 to _g6 .

Therefore, the display portions corresponding to the terminal e10 and the terminal k6 are lit. FIG. 8 shows an outline of the pointer display of this embodiment. In the figure, it can be seen that the seconds hand display section is blinking, indicating the afternoon time.

Note that in the morning, since the terminal q of the detection circuit 25 is "0", the output of the gate circuit 31 is "0", so the switching circuit 28 is turned on, and the potential generated at the terminal _S0 is applied. Therefore, the seconds hand display remains lit.

In this example, only the seconds display was lit, but
It is also possible to blink at least one of the hour and minute display sections. In addition, the display mode of the display section may be any display mode as long as it can be distinguished from other lighting states, so it is not limited to simply blinking, but for example, the lighting time of the seconds display section may be extended, and the lighting state of the next seconds display section may be changed. It is also possible to partially overlap.

Furthermore, the display mode may be changed not only in the afternoon but also in the morning, or only during a specific time.

As described in detail above, the present invention is designed to change the display mode of the display portion corresponding to the pointer during times such as morning or afternoon. Therefore, since there is no need to provide a special display section for indicating the time zone, the number of terminals to be connected to the drive circuit can be reduced. Further, since only a signal for changing the display mode is supplied to the display section, the circuit configuration is simple. Particularly in analog electronic watches with alarms, since morning and afternoon can be clearly distinguished when setting an alarm, there is no risk of making a mistake such as setting the alarm time to a different time than the scheduled one.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention; FIG. 1 is a drive circuit diagram, FIGS. 2 and 3 are plan views showing electrodes and wiring patterns of a liquid crystal display device, and FIGS. FIG. 7 is a circuit diagram showing a part of the drive circuit in detail, FIG. 7 is a potential and voltage state chart showing the operation of the drive circuit, and FIG. 8 is a plan view showing an example of a display. 3, 4...second digit counter, 5,6...minute digit counter, 7,8...hour digit counter, 1
0...Timing pulse generation circuit, 22...Segment potential setting circuit, 23...Common potential setting circuit, 26...Potential setting circuit, 33a...Segment electrode, 34a...Common electrode.

Claims (1)

[Scope of utility model registration request] A plurality of segment electrodes arranged radially are divided into groups of a predetermined number, and corresponding ones of the segment electrodes constituting each group are electrically connected, and a liquid crystal is connected to the segment electrodes of the above group. Opposing common electrodes are provided for each group to constitute a liquid crystal display device consisting of a plurality of display elements, a reference pulse generation circuit for generating a reference pulse is provided, and time is measured by receiving the output of this reference pulse generation circuit. A selection circuit includes a timing pulse generating circuit that receives the output of the reference pulse and generates a timing pulse, and receives the output of the timing pulse generating circuit and selects the digit output of the timing circuit in a time-sharing manner. and at least |Vo|, 2|
A pulse setting circuit is provided to set pulse voltages of Vo| and 3|Vo|, and at least three types of pulse voltages are selected from the pulse setting circuit to all of the segment electrodes and the common electrode according to the output of the selection circuit. a voltage supply circuit that applies a voltage to turn the display element on, partially on, or off;
A detection circuit is provided for detecting AM and PM in response to the output of the clock circuit, and a blinking circuit is provided for controlling the voltage supply circuit using a specific output of the detection circuit to cause a display element for a predetermined display to blink. Electronic clock display device.