JPS62189520A - Clock count system for microcomputer - Google Patents

Abstract

PURPOSE:To guarantee a timing action at the time of power failure by measuring the oscillation frequency of a 2nd oscillator circuit after restoration from power failure with the oscillation frequency of a 1st oscillator circuit as a reference, correcting the count value at the time of power failure according to the result and adding it to the reading of the clock before power failure. CONSTITUTION:Where the value of a counter circuit 4, the oscillation frequency of the 1st oscillator circuit, a value obtained by summing up the values of frequency dividing circuits 5 and 6 and a frequency are A, X Hz, P and (n), respectively, at the time of restoration from power failure, the output of a frequency dividing circuit 7, that is, the time T of one period is expressed by an equation, T=P/XXA/n. If the value counted during power failure is multiplied by the time T obtained by the equation, a pulse (the value of a counter circuit 4) generated by an LC or CR oscillator is corrected to a value at crystal accuracy. Then the corrected value is added to the reading of the timepiece before power failure. Hence onward, the output of a frequency dividing circuit 9 is again counted, and a normal timing action is executed, and the oscillation action of the 2nd oscillator circuit 2 is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock counting method in a microcomputer, and particularly to a method for operating a clock for a long time during a power outage.

[Conventional technology]

Conventionally, in systems in which a microcomputer performs a clock function as part of its functions, there are cases in which a commercial frequency (50Hz or 60H2) is used as the reference signal for the clock, and cases in which an oscillator is constructed using a crystal oscillator and its oscillation output is divided. In some cases, a signal that has been circulated is used.

[Problem that the invention seeks to solve]

Systems that use commercial frequencies as reference signals for clocks have a major drawback in that the clock function stops in the event of a power outage. In addition, systems using crystals divide the oscillation frequency to create a clock of less than 1 second, such as a clock of 500m8, and when a power outage occurs, the CPU is normally stopped, and when the reference signal of the clock of 500m5 is detected, the CPU
A method is used in which the clock is started and the clock is counted up.

In this method, the microcomputer's CPU clock is also generated by sharing the crystal oscillator that generates the clock reference signal.
Served. Since the CPU clock requires a certain high frequency, even if the CPU is operated only when the reference signal of the clock is detected during a power outage, a large amount of current is consumed by the frequency dividing circuit, etc. To guarantee time clock operation, a special large-capacity capacitor or battery is required, which increases costs. A microcomputer using the above-mentioned method usually uses a crystal oscillator of around 30 KHz, and consumes a current of several tens of μA to several hundred μA. Therefore, even if a large capacity capacitor such as an IF is used as a backup capacitor, clock operation can only be guaranteed for a few hours because the guaranteed operating voltage of the CPU of the microcomputer is high.

[Means for solving problems]

Therefore, the clock counting method of the microcomputer of the present invention consists of a first oscillator circuit that includes a crystal oscillator that generates the CPU clock, and an oscillator circuit that includes an LC or C circuit that generates oscillation pulses that can be used as the count clock of the clock in the event of a power outage. a second oscillation circuit forming the circuit, a power failure detection circuit that detects a power failure signal from the outside, a control circuit that controls the operation of the first oscillation circuit by the output of the power failure detection circuit, and an oscillation pulse of the second oscillation circuit. A counter circuit for counting, means for measuring the oscillation frequency of the second oscillation circuit based on the oscillation frequency of the first oscillation circuit, and a counter for counting the oscillation pulses of the second oscillation circuit based on the measured results. and means for correcting the count value of the circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

A crystal oscillator 13 is connected to the oscillation circuit 1, and a CPU clock is generated via a frequency dividing circuit 5. Furthermore, the frequency dividing circuit 5
The output is passed through the frequency divider circuit 62 and the frequency divider circuit 9 to generate a clock reference clock during normal operation.

The output of the frequency dividing circuit 6 is connected to the frequency dividing circuit 9 and also to one input of the input selector 11.

The other input of the input selector 11 is connected to the output obtained by dividing the output of the second oscillation circuit 2 that constitutes an oscillator by the LC circuit 14 by the frequency dividing circuit 7 . The output of the input selector 11 is connected to one input of the gate circuit 10.
The output of the frequency divider circuit 7 is connected to the other input of the gate control circuit 1.
2. The output of the gate circuit 10 is connected to the counter circuit 4, and the count value of the counter circuit 40 is read out to the data memory (RAM) of the microcomputer via the data bus.

Next, the specific operation will be explained.

First, the first power supply (VDD = Hi) is applied to the microcomputer.
gh) is applied to the power outage signal input terminal.
Input the level signal. This state refers to the state in which the set is first connected to an AC source. When a high level signal is input to the power outage signal input terminal, the power outage detection circuit 3
detects this state, and the control circuit 8 outputs a signal that puts the first oscillation circuit 1 into the operating state and the second oscillation circuit 2 into the stopped state. At this time, the second oscillation circuit 2 does not necessarily have to be stopped. In other words, the control circuit 8 may be configured to control only the first oscillation circuit 1, and the second oscillation circuit 2 may be left operating at all times without causing any operational problems.

As a result, the second oscillation circuit 1 starts an oscillation operation, and the output of the frequency divider circuit 5 generates the 9 CPU clock, and the output of the frequency divider circuit 9 generates the reference clock of the clock. If the standard clock of this watch is 100m5, 91 seconds can be created by counting 10 times. When a clock is operated by a microcomputer, a second area is created on the RAM based on the reference clock mentioned above.

This was achieved by adding to the minute area and hour area, carrying, etc. using software.

The above refers to the operating state when electricity is applied, and clock operation with crystal precision can be obtained.

Next, the operating state during a power outage will be explained. The power supply of the microcomputer is backed up by a capacitor or the like, and a low level signal is input to the power failure signal input terminal. The power failure detection circuit 3 detects this state, and the control circuit 8 outputs a signal to stop the first oscillation circuit 1 and to put the second oscillation circuit 2 into operation. This causes only the second oscillation circuit to operate. The silkworm output of the second oscillation circuit 2 is input to the input selector 11 via the frequency dividing circuit 7. The input selector 11 is a switch circuit that connects the output of the frequency divider circuit 7 to one input of the gate circuit 10 or connects the output of the frequency divider circuit 7 to one input of the gate circuit 10.
The output of the frequency divider circuit 7 is connected to one input of the gate circuit 10 during a power outage. The output of the gate control circuit 12 is connected to the other input of the gate circuit 10, and a high level signal is input thereto.

In other words, the output of the frequency dividing circuit 7 is input to the counter circuit 4. Assuming that the output of the frequency dividing circuit 7 is set to a cycle of 200 m8 or more, it is sufficient to configure the counter circuit 4 with a binary counter of about 20 bits in order to guarantee a 24-hour counting operation.

Next, we will explain the operation when the system recovers from a power outage.

When the power is restored from a power outage, the power outage signal input terminal is set to High again.
Input h level signal. At this time, the control circuit 8 outputs a signal that puts the first oscillation circuit 1 into operation. This causes the microcomputer to start operating. After the start, the output of the frequency divider circuit 9, that is, the generation of the clock reference clock, is detected, and after the detection, the gate control circuit 12 closes the gate circuit 10. A low level is output to the output gate circuit 10. In this state, the data of the color/reader circuit 4 is read out and stored in the LRAM.

After detecting the generation of the clock reference clock, the gate circuit 10
The reason for closing is to clarify the power outage period and reduce errors.

Next, one input of the divider circuit 10 is connected to the output of the frequency divider circuit 6 by the input selector 11 . In this state, the gate control circuit 12 controls so that the high level of the output of the frequency dividing circuit 7 for n cycles is applied to the other input of the gate circuit 10. The output of the frequency dividing circuit 6 is inputted to the counter circuit 4 for a time period corresponding to n periods of the output of the frequency dividing circuit 7.

As a result, if the value of the counter circuit 4 is "A", the oscillation frequency of the first oscillation circuit is X Hz, and the total frequency division value of the frequency divider circuit 5 and the frequency divider circuit 60 is P, then the output of the frequency divider circuit 7, that is, The time T for one cycle of the signal is expressed by the following formula.

By multiplying the time calculated by the above formula by the counter value counted during the power outage period, the pulse generated by the LC or C8 oscillator (the value of counter circuit 4) will be corrected to the value with crystal accuracy. Become.

After that, the corrected value can be added to the value of the clock before the power outage. After this, the output of the frequency divider circuit 9 is counted again to perform normal clock operation, and the reason why the oscillation operation of the second oscillation circuit 2 is stopped when the first oscillation circuit 1 is operating is as follows. This is to reduce the chance of causing interference to an external circuit (such as a receiver), and depending on the equipment to which it is applied, the oscillation operation of the second oscillation circuit 2 may not have to be stopped.

In addition, if a number less than the output of the frequency divider circuit 9 occurs in the corrected value, the number of minutes cannot be added to the clock value before the power outage, so an error may occur if the number of power outages increases. become. Therefore, it would be better to store the several minutes that occur due to one power outage, add only the few minutes each time there is a power outage, and correct it when the value exceeds the output of the frequency divider circuit 9. action can be achieved.

Furthermore, since the second oscillation circuit is composed of a C oscillator or an LC oscillator, the voltage reduction characteristics generally deteriorate.

In other words, it is assumed that the oscillation frequency varies due to voltage variation. Therefore, in order to achieve this, a constant voltage power supply circuit may be built in, and the second oscillation circuit may be configured to operate at, for example, 2V.

As mentioned above, the counter circuit 4 requires a binary counter of about 20 bits to guarantee a 24-hour power outage. Therefore, A/
If a D converter, a programmable counter constituting a PLL circuit, etc. are built-in, these circuits can be used in common, and there is no need to provide a special counter circuit.

〔Effect of the invention〕

As explained above, the present invention detects a power outage signal from the outside and stops the oscillation operation of the first oscillation circuit comprised of a crystal oscillator that generates a CPU clock at the time of power outage. The second oscillation circuit is brought into operation and oscillated at a low oscillation frequency of about 100Hz, and its oscillation output is counted by a counter circuit, and after recovery from the power outage, the oscillation frequency of the second oscillation circuit is set to the oscillation frequency of the first oscillation circuit. By measuring based on the frequency, correcting the counter value at the time of power outage using the result and adding it to the clock value before the power outage,
Clock operation can be achieved with low current and voltage, and as a result, long-term clock operation can be guaranteed during power outages. Furthermore, there is no need for special large-capacity capacitors or batteries for backup, and backup can be performed with easily available ordinary electrolytic capacitors, reducing costs.

In addition, since the oscillation frequency of the second oscillation circuit composed of the LC or C1 (, circuit) is corrected by the oscillation frequency of the second oscillation circuit composed of the crystal oscillator, the oscillation frequency of the second oscillation circuit is There is no need for adjustment and inexpensive parts can be used.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1...First oscillation circuit, 2...Second oscillation circuit, 3...Power failure detection circuit, 4......
・Counter circuit, 5゜6.7.9... Frequency divider circuit, 8... Control circuit, 10... Gate circuit, 1 piece... Input Selector, 12...
Gate control circuit, 13...Crystal oscillator, 14.
...LC circuit. plate ゝ

Claims (1)

[Claims] A first oscillation circuit that constitutes an oscillator with a crystal oscillator that generates the CPU clock of the microcomputer, and an LC that generates a signal that can be the count clock of the power outage clock.
Alternatively, a second oscillation circuit that constitutes an oscillator using a CR circuit, a power failure detection circuit that detects a power failure signal from the outside, a control circuit that controls the operation of the first oscillation circuit based on the output of the power failure detection circuit, and the second oscillation circuit. The power outage detection circuit has a counter circuit for counting oscillation pulses of the oscillation circuit, and means for measuring the oscillation frequency of the second oscillation circuit based on the oscillation frequency of the first oscillation circuit, and the power outage detection circuit detects a power outage. When this occurs, the operation of the first oscillation circuit is stopped, the CPU of the microcomputer is put in an inactive state, and the oscillation pulses of the second oscillation circuit are counted by the counter circuit, and the measured second oscillation circuit is counted. A clock counting method for a microcomputer, characterized in that the counter value of the counter circuit is corrected based on the oscillation frequency and added to the clock value before the power outage.