JPS6239396B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power reduction method in a timekeeping device.

In a timekeeping device, for example, a stop watch with an accuracy of 1/10 second generates a clock at 1/10 second intervals, and performs timekeeping operations based on this clock. Further, ordinary watches, timers, etc. generate clocks at one-second intervals, and perform timekeeping operations in accordance with these clocks. By the way, in conventional timekeeping devices, for example, when a stopwatch function with 1/10 second accuracy is added as shown above, the clock is always counted using a 1/10 second clock while the stopwatch is operating, regardless of whether there is a display or not. It's starting to get hotter. However, if the device is equipped with a calculation function, a clock function, etc. in addition to the stopwatch function, there may be times when you want to perform calculations or find out the current time while the stopwatch function is operating and displaying the stopwatch function. be. In such a case, the time display on the stopwatch is temporarily stopped and switched to displaying the current time. In addition, there are other cases where, for example, a stopwatch function is used to measure time over a long period of time, and display during the measurement may not be necessary. In this way, there are cases where the timekeeping contents are not displayed while the stopwatch function is operating, and during this non-display period, the timekeeping operation is performed using the 1 second low speed clock instead of the 1/10 second high speed clock. There is no problem. However, with conventional timekeeping devices, as mentioned above, even when the timekeeping information is not displayed while the stopwatch is operating, the timekeeping is performed using a high-speed 1/10 second clock, which reduces power consumption. The disadvantage is that there are too many.

An object of the present invention has been made in view of the above points, and is to provide a timekeeping device using a microcomputer that reduces power consumption without impairing timekeeping accuracy.

The present invention will be explained below with reference to the drawings. In FIG. 1, reference numeral 1 denotes a key input section, which includes a numeric key 2, a function key 3, a start/stop key 4, a recall key 5, a clear key 6, and the like. The operation output of each key 2 to 6 in the key input section 1 is sent to the ROM address section 7, and this ROM address section 7 specifies the address of a ROM (read only memory) that stores various microprograms. be exposed. Further, the operation output of the start/stop key 5 is sent to a binary counter 9 as a count up signal, and the output of this binary counter 9 is sent to the ROM address section 7 and the AND circuits 10 and 1.
1. Furthermore, the operation outputs of the start/stop key 4 and recall key 5 are OR circuit 1.
2 to the set terminal S of the flip-flop 13
is input to. And this flip-flop 1
The operation output of the clear key 6 and the output of the flip-flop 14 are inputted to the reset terminal R of No. 3 via an AND circuit 15. The Q side output of the flip-flop 13 is input to the flip-flop 14 and the AND circuit 16, and is also input to the inverter 16.
The signal is input to the AND circuit 17 via. Also, 1
8 is a pulse oscillator (PG) that generates a reference pulse signal, and its oscillation output is input to the frequency dividing circuit A. This frequency dividing circuit A divides the reference pulse signal from the pulse oscillator 18 to obtain a 1/10 second signal.
Divide the frequency of the 1/10 second signal output from the second frequency dividing circuit 19 and this 1/10 second frequency dividing circuit 19 to obtain a 1 second signal.
It consists of a decimal counter 20. And 1/10
The output of the second frequency dividing circuit 19 is input to the AND circuit 15, and the output of the decimal counter 20 is input to the AND circuit 17. The outputs of the AND circuits 15 and 17 are passed through the AND circuits 10 and 11, respectively.
It is sent to the ROM address section 7. This ROM address section 7 receives signals input from AND circuits 10 and 11 or signals from the key input section 1.
Specify the address of ROM8 according to the next address NA from ROM8. This ROM8 is equipped with output lines a to e, and from output line a, the RAM
(Random access memory) 21 outputs address data U specifying a row address, and output line b outputs address data L specifying an example address of RAM 21. Further, the ROM 8 outputs a numerical code code from the output line c, various instructions INS from the output line d, and the next address NA from the output line e. RAM2 above
1 is equipped with an X register, a Y register, etc. for various calculations, and an ST register for a stop watch as shown in FIG. This ST register has a 7-digit configuration, where the 0th digit stores 1/10 second data, and the 1st to
The second digit is used to store seconds data, the third to fourth digits are used to store minute data, and the fifth to sixth digits are used to store hour data. Thus, the data read from the RAM 21 is input to one input terminal a of the arithmetic circuit 22. Further, the code signal code outputted from the output line c of the ROM 8 is input to the other input terminal b of the arithmetic circuit 22 via the gate circuit 23, and the count contents of the decimal counter 20 are input to the gate circuit 24. Input via . The calculation result output from the calculation circuit 22 is
The data is sent to the display unit 25 and RAM 21. moreover,
The instruction INS output from the output line d of the ROM 8 is sent to the instruction decoder 25. This instruction decoder 25 decodes instructions from the ROM 8, and sends various control commands such as read/write signals R/W to the ROM 21, subtraction command Sub to the arithmetic circuit 22, and gate signals to the gate circuits 23 and 24.
Then, a reset signal is input to the binary counter 9. This reset signal to the binary counter 9 is given when the power is turned on.

Next, the operation of the present invention configured as described above will be explained. When the power is turned on, a reset signal is output from the instruction decoder 25 in accordance with the instruction INS from the ROM 8, and the binary counter 9 is reset. As a result, the output of the binary counter 9 becomes "0", and the AND circuit 10,
Gate No. 11 is closed and the operation of the stopwatch function is prohibited. In this state, when the ST key 4 is operated as shown at 1 in FIG. 3, the operation output is sent to the flip-flop 13 via the OR circuit 12. As a result, the flip-flop 13 is set and a "1" signal is output from its Q side output terminal, and the gate of the AND circuit 15 is opened. this
The data is sent to the ROM address section 7, and the address designation of the ROM address section 7 causes the operation control of the ROM 8 to be set to the stopwatch operation mode. Also,
The operation output of the ST key 4 is sent to the binary counter 9, and its contents are incremented by 1. Therefore, the output of the binary counter 9 becomes "1", and the AND circuits 10 and 11
gate will be opened. Furthermore, the operation output of the ST key 4 is inputted to the set terminal S of the flip-flop 13 via the OR circuit 12. As a result, the flip-flop 13 is set, and a "1" signal is output from its Q side output terminal, and the AND circuit 1
Gate 5 will be opened. At this time, inverter 1
6 becomes "0", and the AND circuit 17 closes its gate. Therefore, the 1/10 second signal output from the 1/10 second frequency dividing circuit 19 is input to the ROM address section 7 via the AND circuit 15 and the AND circuit 10. When this 1/10 second signal is input to the ROM address section 7, the row address U and column address L are output from the ROM 8 according to the address specification of the ROM address section 7, and the 0th digit of the ST register in the RAM 21 is is specified. Further, a code signal of numerical value "1" is output from the output line c of the ROM 8 and sent to the arithmetic circuit 22 via the gate circuit 23. Then, by this arithmetic circuit 22, the above
"1" is added to the data read from the 0th digit of the ST register. At this point, the content of the 0th digit of the ST register is "0", so the arithmetic circuit 2
2, an addition operation of "0+1=1" is performed, and the addition result is written to the 0th digit of the ST register. That is, as shown in FIG. 3, 1/10 second is added to the 0th digit of the ST register. If a carry signal is generated by this addition operation, ST
Carry processing is performed on the upper digits of the register. The time measurement data thus added by the arithmetic circuit 22 is sent to the display section 25 and displayed as shown in FIG. 31. At this point, 1/10 second timing data is displayed. Further, the 1/10 second signal outputted from the 1/10 second frequency dividing circuit 19 is sent to the decimal counter 20, and its contents are counted up by "1". Similarly, from 1/10 second frequency dividing circuit 19 to 1/
Every time a 10 second signal is output, 1/10 second is added to the ST register in the RAM 21, and the contents of the decimal counter 20 are sequentially incremented by 1. After a predetermined period of time has passed, if the ST key 4 is operated as shown in FIG. 3, the contents of the binary counter 9 will be +1.
and returns to the reset state. Therefore, the output of the binary counter 9 becomes "0", and the AND circuits 10 and 1
The gate No. 1 is closed, and input of the clock clock to the ROM address section 7 is prohibited. As a result, the timekeeping operation of the stopwatch is temporarily interrupted. At this time, if the contents of the ST register in the RAM 21 are "123", the display section 25 will appear as shown in FIG.
The timing data of "12.3" seconds is displayed. In this state, if the ST key 4 is further operated as shown in FIG.
11. For this reason, 1/10 second frequency dividing circuit 19
The 1/10 second signal output from the ROM address section 7 is again sent to the ROM address section 7, and the stopwatch restarts the timekeeping operation. At this time, since the stopwatch's timing operation has temporarily stopped, the contents of 1/10 second in the 0th digit of the ST register and the decimal counter 2
Although the contents of 0 will be different, as the binary counter 9 changes from "0" to "1" by operating the ST key 4, the output is output from the binary counter 9 to the ROM address section 7. A signal is sent, the difference between the contents of the 0th digit of the ST register and the contents of the decimal counter 20 is calculated, and the RAM 21
The difference is stored in a predetermined register within. Therefore, as shown in FIG. 3, when the stopwatch restarts, the 0th digit of the ST register is "3" and the decimal counter 20 is "5", so the difference between the two is "2". ”. The calculation result "2" is written to the 0th digit of the ST register as the correct value for the 1/10 second digit when the timekeeping operation is restarted. When the stopwatch function is in operation, if the display is to be temporarily interrupted to perform another operation, such as an arithmetic operation, the clear key 6 is first operated as shown in FIG. The operation output of this clear key 6 is sent to the ROM address section 7, and the ROM address section 7 specifies the address.
A control command is issued from 8, and switching to the calculation mode is performed while the stopwatch function continues to operate. Therefore, the contents of the X register in the RAM 21 are sent to the display section 25 and "0" is displayed. At the same time, when the clear key 6 is operated and its operation output is input to the AND circuit 15, the output of the AND circuit 15 becomes "1" and the flip-flop 13 is reset. Therefore, the signal output from the Q side output terminal of flip-flop 13 is "0".
Then, the gate of the AND circuit 15 is closed. Further, at this time, the output of the inverter 16 becomes "1", and the gate of the AND circuit 17 is opened. As a result, the 1 second signal output from the decimal counter 20 is sent to the ROM address section 7 via the AND circuits 17 and 11, and as shown in FIG. calculations are performed. Note that the 0th digit of the ST register remains the count value "7" at the time the AC key was operated. In this state, by operating the numeric key 2 and function key 3 in the key input section 1, the specified operation is performed in the X, Y registers in the RAM 21 and the arithmetic circuit 22, and the result of the operation is written to a register. The data written in this X register, for example "3456", is then sent to the display section 25 and displayed.

After the above calculation is completed, if the time data of the stopwatch is to be displayed on the display section 25 again, the recall key 5 is operated. When the recall key 5 is operated as shown in Fig. 3, the operation output is
The data is sent to the ROM address section 7, and according to the address specification, the contents of the ST register in the RAM 21 are sent again to the display section 25 and displayed. Further, from the instruction decoder 25 to the gate circuit 24
A gate signal is sent to the decimal counter 24, and the contents of the decimal counter 24 are sent to the arithmetic circuit 22 via the gate circuit 24. Then, in this arithmetic circuit 22, correction of the 1/10 second digit, which is the 0th digit of the ST register, is performed.
That is, the content "4" of the decimal counter 20 is stored in RAM2.
1 is subtracted by the difference "2" stored in a predetermined register, and the subtraction result "2" is written to the 0th digit of the ST register as the correct value. In addition, in the calculation for this correction, the contents of the decimal counter 20 at the time of correction depend on which value is larger when calculating the difference between the 0th digit of the ST register and the contents of the decimal counter 20. It is selected whether to add or subtract the difference. Further, the operation output of the recall key 5 is inputted to the set terminal S of the flip-flop 13 via the OR circuit 12. Therefore, the flip-flop 13 is set, and a "1" signal is output from its Q side output terminal.
The gate of AND circuit 15 is opened. At this time, the output of the inverter 16 becomes "0", and the AND circuit 1
Close gate 7. Therefore, 1/10 second frequency divider circuit 1
The 1/10 second signal output from 9 is sent to AND circuit 15,
10 to the ROM address section 7, and the 0th digit of the ST register is incremented by 1. In this way, the stopwatch function again starts measuring time in units of 1/10 seconds. In addition, the stopwatch function is
By operating the clear key 6 while the stopwatch has stopped measuring time by operating the ST key, the timekeeping operation is ended and the timekeeping contents are cleared.

In the above embodiment, the 1 second signal and the 1/10 second signal are used, but for example, in a stop watch with 1/100 second accuracy, the 1 second signal and the 1/100 second signal may be used. The present invention is not limited to the above embodiments.

As described above, according to the present invention, during the operation of a function such as a stopwatch, in the non-display mode in which the time measurement contents are not displayed, the low-speed clock that is the output of the second frequency dividing circuit (decimal counter 20) is Since the time measurement process is performed using the , power consumption for the time measurement process during non-display can be reduced.

In addition, in the case of display mode, the first frequency dividing circuit 19
The high-speed clock that is the output of is used for timekeeping processing, and when the mode changes from non-display mode to display mode, the difference between the content of the second frequency dividing circuit and the digit part of the corresponding timekeeping content is added to the timekeeping content. Since the correction is made, there is no loss in timing accuracy.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is a circuit configuration diagram, FIG. 2 is a diagram showing the configuration of a stopwatch register in the RAM in FIG. 1, and FIG.
FIG. 3 is a diagram showing changes in register contents and display contents due to key operations. 1...Key input unit, 4...Start/stop (ST) key, 5...Recall key, 6...Clear key, 8...ROM, 21...RAM, 23, 24...Gate circuit.

Claims (1)

[Claims] 1. A first frequency divider circuit that divides a reference frequency signal and generates a high-speed clock; and a circuit that is connected to the output terminal of the first frequency divider circuit and counts its output to generate a low-speed clock. a second frequency divider circuit, and a timekeeping means using a microcomputer that performs timekeeping processing based on the high-speed clock or the low-speed clock;
mode designation means for designating a display mode for displaying timed contents and a non-display mode for not displaying the timed contents;
display means for displaying time measurement contents from the time measurement means in response to a command from the mode designation means, and individually receiving outputs from the first and second frequency dividing circuits;
A high-speed clock of a first frequency dividing circuit is supplied to the timekeeping means in response to a display mode signal from the mode designation means, and a second clock is supplied to the timekeeping means in response to a non-display mode signal from the mode designation means. selecting means for supplying a low-speed clock to the second frequency dividing circuit; and receiving a command from the mode specifying means, and selecting the contents of the second frequency dividing circuit in response to the change from the non-display mode signal to the display mode signal. and an addition means for adding the difference between the time measurement contents of the time measurement means corresponding to the time measurement means to the time measurement contents of the time measurement means, and in the non-display mode, time measurement processing is performed using a low-speed clock to reduce power consumption. timing device.