JPS6032625Y2 - timing circuit - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a timekeeping circuit that enables counting operations using only one counter.

Conventional timekeeping circuits such as electronic watches require many counters.

For example, there are a seconds counter, a minute counter based on its output, and an hour counter based on its output, and these counters usually have multiple stages of circuits called frequency dividers that reduce the frequency to 172. Most of them were connected to.

Now, to explain the conventional timekeeping circuit, FIG. 1 shows it. In this FIG.
It is composed of various counters such as a day counter 6, a week counter 7, and a month counter 8.

As shown in FIG. 1, the oscillation circuit 1 generally used includes an inverter 1a as an amplifier whose input and output are connected by a bias resistor IF, a crystal resonator CRY as a feedback circuit, and a Correction capacitor C
G, I am more careful than Cd.

The frequency oscillated by this oscillation circuit 1 is divided by the frequency divider circuit 2, but the frequency that is commonly used these days is 32768H2, so in this case, by dividing the frequency by 1, the output side is I am getting IH2.

Various frequency dividing circuits have been considered for use in this case, and one example is the circuit shown in Figure 2.
Further, the various counters 3 to 8 shown in FIG. 1 are also generally constructed from frequency dividing circuits as shown in FIG. 2.

For example, in the case of second counter 3, it repeats counting up to 1/60H2 (6@) based on the input of IH2, and the other counters are also similar.

Thus, conventional systems require many counters.

This idea was developed in consideration of the above points, and it is possible to reduce the pattern size by making it possible to operate with only one counter, and also to use one integrated circuit chip in conjunction with other systems, such as calculators. In this case, the present invention provides a time measurement circuit that can be shared with other systems such as an adder and a RAM (read/write memory) in a time-sharing manner, and has the advantage of being highly versatile.

Hereinafter, an embodiment of the clock circuit of this invention will be explained. FIG. 3 is a block diagram showing one embodiment. In this FIG. The output drives the counter 13. In this case, the output of the oscillator 11 may be used as an accurate lock signal to drive the counter 13.

The output of the counter 13 is sent to a decoder 14, and the decoder 14 receives the output of the counter 13 and outputs an output for controlling the adder 15, accumulator 16, determination circuit 17, and RAM 1f3.

If the RAM 1B (or flip-flop circuit) is to perform the same function as that shown in FIG. 1, then FIG.
A2. AoA8. B1. B2. B is second memory, C1
, C2, CoC8, Dl, D2. D, minute memory 1EI
IE2? E49E8. Fl is time memory, G1°G2.
G,, C8, Hl, B2. Day memory, ■1. I2
．． ■,.

is weekly memory, J,, J2. The same number of memories are required, as shown in Figure 6 (showing an example of RAM 1f3 in Figure 3), for example, the memory in this case. It is easy to understand that this cell has a smaller pattern size than the frequency divider shown in FIG.

In addition, in this case, the adder 15, the accumulator 16 and the R
The relationship between AM1f3 is shown in FIG.
The contents of 8 are sequentially selected by the output of the decoder 14,
The four bits of selected memory are loaded into accumulator 16.

The contents of this accumulator 16 are + by the adder 15.
1, the data is read into the accumulator 16 again, and then the content of the accumulator 16 is cleared by the judgment circuit 17 and the data is stored in the RAM l fJ.
or determine whether to write to accumulator 1
After determining whether to write the contents of 6 to RAMI as they are, when the next instruction should be executed, in other words, a carry occurs and +1 is written to the memory above the -rise.
When necessary, the RAM 18 is newly designated by the decoder 14 and read out to the accumulator 16.

In addition, when it should not be executed, the RA by the decoder 14
Prohibits reading from MI to accumulator 16.

A flowchart showing a specific example of such an operation is shown in the fifth section.
The one shown on the left of Figure 5 is the one in which the code on the left corresponds to the instruction on the right among the combinations of outputs 1 to I6 of the counter 13, so that the code progresses sequentially from the top. Make it.

In this case, a case is considered in which a clock is applied to the counter 13 from the oscillator 11 or the frequency dividing circuit 12 every 2''64 seconds, and the output of the counter 13 changes.

As a means of generating codes that progress sequentially in response to instructions, we have been using a counter that is driven by the output of a frequency-divided oscillator. It goes without saying that the counter can be used as a program counter and the read-only memory can be used as a means for generating codes that progress sequentially in response to instructions.

As described above, according to this invention, since only one counter performs the counting operation, the timekeeping circuit can be configured with an extremely versatile circuit, and has the advantage of being able to be shared with other systems by time sharing. be.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional timing circuit, Fig. 2 is a circuit diagram of a frequency divider in the conventional timing circuit, Fig. 3 is a block diagram showing an embodiment of the timing circuit of this invention, and Fig. 4 is a block diagram of a conventional timing circuit. FIG. 5 is a flowchart showing the operation when the system of the timing circuit shown in FIG. 3 is executed, and FIG. FIG. 7 is a diagram showing an example of the RAM in the timekeeping circuit, and is a diagram for explaining the operation of the portion after the counter in the timekeeping circuit of FIG. 3. 11... Oscillator, 12... Frequency divider circuit,
13... Counter, 14... Decoder, 15... Adder 16... Accumulator, 17... Judgment circuit, 8...・RAM0

Claims (1)

[Scope of utility model registration request] A counter driven by the output of an oscillator or an output obtained by dividing the output of this oscillator, a decoder that decodes the output of this counter, and the memory contents are sequentially selected by the output of this decoder and read into an accumulator for each predetermined bit. A RAM that writes the contents of the accumulator, an adder that increases the contents of the accumulator by 1 based on the output of the decoder each time the contents of the RAM are read into this accumulator, and an RA that is controlled by the output of the decoder.
This timekeeping circuit comprises a determination circuit that determines whether to read the contents of M and clear the accumulated contents of the accumulator and write them into the RAM, or whether to write them to the RAM while leaving the contents of the accumulator as is.