JPS608470B2 - Timekeeping method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timekeeping system controlled by a microprogram.

Conventional electronic watches generally use a timekeeping method in which a one-second signal is obtained by dividing the oscillation output of a crystal oscillator or the like that oscillates at the fundamental frequency, and this is sequentially counted by a binary counter.

However, since this type of timekeeping method requires extremely complex logic circuits that cannot be multi-functionalized, methods have been developed in recent years to control the clock using microprograms stored in ROM (read-only memory), etc. . On the other hand, in recent years, various methods have been attempted in which an electronic calculator is provided with a timekeeping function and this timekeeping function is controlled using a microprogram that controls the above-mentioned computer.

However, if such a timekeeping method uses a shift register or the like and operates in units of words, it is necessary to have a preliminary counter count each time a predetermined number of words are processed, and use the results to accurately measure time. is possible, but
For example, if a RAM or the like is used as a storage device and one processing time is undefined, adopting a clocking method such as the shift register described above will increase the number of processing steps, resulting in the exclusive use of ROM. The disadvantage is that the area becomes large.

In addition, in cases where the processing time is uncertain, the series of processing currently being executed is temporarily interrupted by a pulse output from the frequency divider in each reference time unit, and the address at the time of return is stored in a predetermined storage device. I had to go through a process of post-timekeeping. As a result, for example, computers with a timekeeping function tend to have disadvantages such as different processing times for calculations and different display duties for each digit. On the other hand, when the timekeeping status is displayed using a timekeeping device or a calculator with a timekeeping function, the actual time and the displayed time must match, but when a small electronic calculator with a timekeeping function is used as a calculator, the timekeeping time is If this is not the case, the internal timekeeping does not necessarily have to match the actual time;
When displaying the measured time, it is sufficient if it matches the actual time.

- The present invention has been made in view of the above circumstances, and includes: ``a holding means for holding a timing pulse outputted from a minute unit in each reference timing unit, and an output of the holding means is detected after a predetermined process is completed. It is an object of the present invention to provide a timekeeping method that eliminates the above-mentioned drawbacks by measuring time using the following methods.

An embodiment in which the present invention is applied to a computer with a timekeeping function will be described below with reference to FIGS. 1 to 4.

FIG. 1 explains the configuration of this embodiment. 1 is a circuit block diagram for the purpose of the present invention, and numeral 1 in the figure is a reference signal oscillator such as a crystal oscillator. The output of this reference frequency oscillator 1 is applied to a frequency divider 2, and the frequency divider 2 divides the output of the reference frequency oscillator 1 and outputs a 1 second signal (a signal output every 1 second). , this turtle sand signal is applied to the set terminal S of the selection S flip-flop 4 via the one-shot circuit 3,
Every time a 1 second signal is output, this R-S flip-flop 4
Set. And this R-S flip flop.
The Q side (set side) output of 4 is applied to an AND circuit 5.

On the other hand, 6 is a storage unit that permanently stores microprograms that control the operation of each circuit.
I am using OM. Therefore, from this ROM 6, there is a RAM that stores various data for calculations or timekeeping.
8, an operation signal that specifies the operation of each circuit, a code such as a numerical value necessary for calculation or time measurement, and a next address signal that specifies the next address of the bus line B, each consisting of complex bits; &
, & and B4. Bus line B4
The next address output via the AND circuit 5 is applied to the ROM address unit 7 which specifies the address of the ROM 6, and the ROM 6 selects the micro memory stored in the address output from the ROM address unit 7. The program is output via the respective bus lines B to B4. Further, the data in the RAM 8 designated by the address signal applied via the bus line B is outputted via the bus line B5 and input to the arithmetic circuit 9.

The arithmetic circuit 9 executes various operations using the data input from the RAM 8 or the code input via the bus line B3, and sends the results to the RAM 8 via the bus line B6.
The signal is output to an OR circuit 10 and a display buffer (not shown). Therefore, the output of the OR circuit 10 is stored in the data judgment latch 11a of the judgment latch circuit 11, and the carry and borrow from the arithmetic circuit 9 are stored in the judgment latch 11a.
is stored in the carry and borrow determination latch 11b. Each output of these judgment latches 11a and 11b is connected to the ROM address section 7 through a predetermined logic circuit (not shown).
By changing the next address applied to the bus line &, the ROM address section 7 outputs an address different from the next address. Further, 12 is a buffer register that temporarily stores input from a key input section (not shown), and its output is applied to an AND circuit 13 via bus line B, and the output of this AND circuit 13 joins the bus line horse. do.

Furthermore, the bus line B is also applied to the AND circuit 15 via the OR circuit 14, and the output of this AND circuit 15 is applied to the ROM.
It is applied to the address section 7. Each of the circuits described above is controlled by the operation signal outputted via the bass litho string being decoded and outputted by the operation decoder 16.

That is, from the operation decoder 16 to the reset terminal R of the R-S flip-flop 4 via the signal line 02, to the asode circuits 5 and 15 via the signal line 02,
Furthermore, control signals are applied to the AND circuits 13 through the signal line 03 to control the opening/closing of the gate circuits and the setting of the flip-flops. In addition to the above-mentioned signal lines ○ and 03, a plurality of control signal lines 04 to 03 are provided from the operation decoder 16 to output various control signals. Next, the overall operation of this embodiment will be explained with reference to the flowchart shown in FIG. If the ROM 6 now outputs a "HALr' (standby state) command as shown in process A," the operation decoder 16 outputs "1" via the signal line 02, and the AND circuits 5 and 15 1 second signal is output and R
-S When the flip-flop 4 is set or a predetermined key of the key input section is operated and the output is output from the buffer register 12, the address is changed in the ROM address section 7 and the process shown in FIG. 2 is performed, A2 or A4. Proceed to.
That is, when the process A is in the "HALT" state, the band circuit 5
When there is an output from the AND circuit 15, the "key sampling" of the process A4 is performed. When there is an output from the AND circuits 5 and 15, the "key sampling" of the process A3 is performed. After executing "timekeeping related calculations", each "key sampling" of the processing is executed. By executing "key sampling" in process A4, the key operated on the key input section is detected,
If the key is a numeric keypad, if it is a function key for "calendar number processing" in process A5, process Z,
"Various calculations such as four-deposit calculations" are executed and the process proceeds to process A7. In this process A7, the contents of the display register in the RAM 8 are transferred to the display buffer, and then the process returns to "HALr" in process A. On the other hand, after executing process A2, the process advances to process A8,
It is detected whether or not to display the time measurement contents by, for example, determining a flag stored in the RAM 8. If the time measurement contents are to be displayed, go to the process, and if not, proceed to the process A, "HALT". ” Return to

Next, with reference to the flowchart in FIG. 3, the processing in FIG. 2 and the "timekeeping related calculation" in A3 will be explained in more detail.

That is, when the one-second signal is output from the frequency divider 2, the one-shot circuit 3 outputs a trigger pulse synchronized with the rising edge of the one-second signal to set the R-S flip-flop 4.

Therefore, the Q side output of this R-S flip-flop 4 "
1” is applied to the AND circuit 5, and now the signal 02 is “1”
Therefore, the AND circuit 5 outputs “1” and the ROM
An address change signal is applied to the address section 7, and the process proceeds depending on whether or not there is an output from the AND circuit 15. Then, when the processing proceeds to A3, "1" is output from the signal line ○ of the operation decoder 16, as shown in step S in FIG. is set in a state where it can accept the next one-second signal, and then the process proceeds to step S2 to measure time. The RAM 8 is composed of an arithmetic register, a time register, etc., and in this embodiment, for convenience, the time register is referred to as "A," the date register as "B," and the display register as "C." Also, this time register “
AJ and date register "B" are stored in the form of seconds and days, respectively. However, in step S2, the ROM
6 outputs an address specifying register "A" in RAM 8, and the contents of register "A" are read from RAM 8 to arithmetic circuit 9. At this time, operation decoder 1
6 outputs an "addition instruction", and a code "1" is output to bus line B3. Therefore, the calculation circuit 9 executes the calculation "A+1", and the result is stored again in the RAM 8 via the bus line B6. When this process is completed, the process proceeds to step S3, where it is determined whether the contents of the register "AJ" are "86400" or not.
This "8640O" is a value of "24 x 3600",
If it is specially made in 24 decimal notation, it is determined whether or not one day's worth of time has been measured. In this case, bus line B as above
The address specifying the register "A" of RAM 8 is output via the arithmetic circuit 9, and the data of this register "A" and the code "86400" output via the bus line B3 are subtracted, and the result is "0". ” is determined. In other words, the output of the arithmetic circuit 9 is input to the 2-bit judgment lunches 11a and 11b, and if the result of the above operation is "0", the latches 11a and 11b are "0".
, 0", and if there is a mismatch, "1, 0" or "
1, 1'' is stored, and the ROM address section 7 determines the next address to proceed to based on this state. If the above subtraction result is "0", that is, the judgment result is "YES", then the process advances to step S4, and "IJ" is added to the register "B" storing the date.The operation at this time is Almost the same as "A+1" above, the address given via bus line B specifies register "B".

When this step S4 is completed, the process proceeds to step S5 and clears the register "AJ." This clearing operation can be done, for example, by writing "0" into the register "A" or by reading the contents of the register "A" from the contents of the register "A". This is done by methods such as subtracting the amount. When this step is completed, the process proceeds to step A9, where the contents of the register "A" are converted into a display format, ie, "hours, minutes, seconds" and stored in the display register "C".
Furthermore, when a "NO" determination result is obtained in step S3, the next process is executed and the process ends. Next, the relationship between the R-S flip-flop 4 and actual processing will be explained with reference to the time chart of FIG.

FIG. 4A shows a case where the time measurement contents are displayed, and is a case where processes A, A8, and A7 in FIG. 2 are executed. That is, when a 1-second signal is output from the time divider 2 in the "HALT" state of "Processing A" as shown in A-1 of FIG. The trigger pulse is output as shown in A-2, and this trigger pulse is applied to the set terminal S of the R-S flip-flop 4, so that the R-S flip-flop is output at time L as shown in A-3. The Q side output is applied to the ROM address unit 7 via the AND circuit 5.The ROM address unit 7 thereby receives the head address of processing A2, that is, step S in FIG.
Even though the series of processes shown in FIG. 3 are performed, the R-S flip-flop 4 is reset in step S. However, the series of processes shown in FIG. 3 ended at time 8, and processes 8 and A? is executed, the contents of display register "C" are transferred to the display buffer and displayed on a display device (not shown). Hereinafter, the "HALr" state of process A continues until the R-S flip-flop 4 is set, and the same timing operation as described above is performed at times t4 and ts. In this way, "in the example shown in FIG. 4A, time measurement is performed immediately when the 1 second signal is output, and the content of the time measurement is displayed.

Furthermore, FIG. 4 and 8 show a case where the calculator is used simultaneously while operating the timekeeping function. Even if step 4 is set, no timekeeping operation is performed while processing on the computer side is being executed.

That is, at the time, a one-second signal is output from the divider 2 as shown in B-1 of FIG.
The trigger pulse via R-S flip-flop 4
Even if it is set as shown in B-3, “calendar number processing”
In other words, the thin number processing which is assumed to be executing process A5 in FIG.
” immediately proceeds to processing, and a time measurement operation is performed between times t8 and t9. However, since it is currently being used as a computer, processing A, as a result of the judgment of processing &,
Then, if any function key is operated next, proceed to "HALr" of process A.
Proceeding from the r' state to key sampling in process A4, ``key sampling is performed between time t, .''.
Since the key operated now is a function key, the process advances to step A6 and predetermined calculations are performed for t, . ~t.
It will be executed between 2. The 1-second signal output during this execution is held by the R-S flip-flop, and a timing operation is performed between t,2 and t,3 after the completion of processing A6. Therefore, when used as a calculator, the measured time may not match the actual time, but since normal arithmetic processing completes within about 1 second at most, there is no chance of a counting error occurring. There isn't. For example, time ratio. If you operate the key that displays the time measurement contents at step 4, the sampling of this key will be from time t, 4 to t.
, 5, and the resulting processing proceeds to display the contents of the timekeeping register, i.e., register "A".
A transfer operation is performed between times t,5 and t,6, and the contents of the display register "C" are processed and sent to the display buffer for display. The contents displayed at this time match the actual time since the time measurement has already finished. Thereafter, the timekeeping contents continue to be displayed, and as explained in FIG. 4A, the timekeeping is performed without delay to the actual time, and the timekeeping contents are displayed in the evening, matching the actual time. In the above embodiments, the present invention is applied to a computer with a timekeeping function. However, the present invention is not limited to this, and can be widely used in all timekeeping devices controlled by microprograms. This is effective for items with multiple functions and undefined processing time.

Further, in the above embodiment, the 1 second signal was used as the standard time measurement unit, but the present invention is not limited to these, and the present invention
It goes without saying that the reference time measurement unit may be a timer pulse such as 1/10 sand or 1/10 sand.

In addition, ``In the above embodiment, a ``HALT'' of process A is provided, and the process proceeds from process A to the timekeeping operation, but the timekeeping operation is not limited to this. The output of the holding means is detected and processed at a place where the series of processes is not interrupted, such as between a series of processes It's fine as long as it's something.

As explained in detail above, according to the timekeeping method of the present invention, by retaining the timekeeping pulse output for each reference timekeeping unit, even if the above-mentioned timekeeping pulse is output during execution of a continuous series of processes, the above-mentioned There is no need to interrupt the processing of the luck, and the control becomes extremely easy.
As a result, the area occupied by the microprogram storage device such as OM can be reduced, and the calculation time does not depend on whether or not the above-mentioned timing pulse is output.Furthermore, when the timing contents are displayed, the actual It has various advantages, such as being able to appear as if it coincides with the time of day.

BRIEF DESCRIPTION OF THE DRAWINGS The drawings show one embodiment of the present invention; FIG. 1 is an overall circuit block diagram, FIG. 2 is a flowchart for explaining the overall operation, and FIG. 3 is for explaining the timekeeping operation. FIG. 4 is a time chart for explaining the operation of the R-S flip-flop for timekeeping operation.

1... Reference frequency oscillator, 2... Frequency divider, 4...
...R-S flip-flop, 6...R
OM, 7...ROM address section, 8...RAM
, 9... Arithmetic circuit.

ice diagram 2 3rd figure figure Six ．． work figure size * ■ figure size Six

Claims (1)

[Claims] 1. In a timing device that divides the output of a reference frequency oscillator to generate a timing pulse to be output in each reference timing unit, and measures this timing pulse under the control of a microprogram, a holding means for holding the timing pulse. and detecting means for fixedly detecting the holding output of the holding means when a series of processing by the microprogram is finished or during the series of processing, and the detecting means causes the holding means to hold the clock pulse. A timekeeping method characterized in that a timekeeping operation is performed when it is detected that the