JPH034948Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to an electronic timepiece that can efficiently switch modes.

[Prior art]

2. Description of the Related Art Conventionally, electronic watches have been known which have a plurality of other function modes in addition to a basic watch mode, and which are sequentially switched and displayed cyclically each time a single mode changeover switch is operated.

For such electronic watches, when you switch to another function mode and operate another switch to perform a predetermined function, the next time you operate the mode changeover switch, it does not shift to the next mode, but instead switches to the basic watch mode. There is also a function with an added function (hereinafter referred to as a direct return function).

[Problems with conventional technology]

However, for functions such as stopwatch and world clock, it is extremely convenient to return to the basic clock mode by operating the display changeover switch once using the direct return function, but for example, when using multiple alarm modes, If equipped with alarm mode, you can continuously preset the alarm time, turn on the alarm, and
It is necessary to perform OFF control, but in such a case, operability would be extremely poor if the direct return function returned to the basic clock mode every time one alarm mode was set.

[Purpose of invention]

This invention was developed against the background of the above-mentioned circumstances, and its purpose is to provide an electronic watch that can efficiently switch modes with a single mode switch even if it is equipped with a direct return function. It's about doing.

[Key points of the idea]

In order to achieve the above-mentioned purpose, this invention
If an electronic watch with a direct return function is in stopwatch mode, etc., if a switch other than the display changeover switch is operated and a predetermined function is executed, the display changeover switch will return to basic watch mode. When the function of the other switch is not being executed, the display changeover switch is operated to move to the next mode, while in alarm mode, etc., when the display changeover switch is operated, the function of the other switch is executed. The main point is that the mode is moved to the next mode regardless of the situation.

[Configuration of Example]

This invention will be specifically explained below based on an embodiment shown in the drawings. FIG. 1 is a block circuit diagram showing the circuit configuration of a microprogram controlled electronic wristwatch with a direct return function. For example, the reference clock signal of 32,768Hz, which is constantly output from the oscillation circuit 1, is converted to 512Hz by the first frequency divider circuit 2.
The frequency is divided up to 1, and is applied to the second frequency dividing circuit 3.
This second frequency dividing circuit 3 has 8 bits (256, 128,
It consists of a binary counter (64, 32, 16, 8, 4, 2 Hz), and outputs a signal a every 1/2 second when it reaches "00000001". This signal a is input to the timing generator 4, which operates accordingly and outputs various timing pulses based on the output of the oscillation circuit 1 to operate each circuit. The signal a is also input to the address section 5, which specifies a predetermined address in a ROM (read only memory) 6 to start timekeeping processing. Further, when a key provided in the input unit, which will be described later, is operated, a key operation signal b is output from the input unit 7, and is input to the timing generator 4 as an operation start signal, and at the same time, is input to the address unit 5. As a result, the key processing program corresponding to the operation key in the ROM 6 is addressed and key processing is performed.

ROM6 stores microprograms that control all operations of this electronic watch, and includes microinstructions.
Outputs ADDR, DO, NA, and OP in parallel. The microinstruction ADDR is input as address data to a RAM (random access memory) 8, and is also input to an input section 7 and a display section 9. Further, the microinstruction DO is input to the multiplexer 10 as a numerical code. The data from the input section 7, the contents of the second frequency dividing circuit 3, and the output data of the RAM 8 are also input to the multiplexer 10.
The operation number and the operand are switched and output at various processing timings, and the operation unit 11 and the temporary register 12
given to. In this case, the data held in the temporary register 12 is transferred to the multiplexer 1
It is given to the calculation unit 11 in synchronization with the output data of 0. Further, the microinstruction NA is input to the address section 5 as next address data for reading out various microinstructions necessary for the next process, and furthermore,
Microinstruction OP is operation decoder 13
This is the operation data input to the .

The arithmetic section 8 executes key input processing, timekeeping processing, etc., and the resulting data is sent to the address section 4 and
Input to RAM8. Here, the address section 5 is
Convert the address of ROM6. Also, RAM8
The data read in is read out at each processing timing and input to the multiplexer 10 as well as to the display section 9 and the buzzer drive circuit 14.

Operation decoder 13 is a microinstruction
It decodes the OP and outputs various control signals _C1 to _C8, etc., and provides them to each circuit.

Next, the configuration of the display section 9 and the functions of the switches will be explained with reference to FIG. In addition to the basic clock mode, the electronic watch of this embodiment has a plurality of other function modes, such as alarm 1 mode, alarm 2 mode, alarm 3 mode, alarm 4 mode, date alarm mode, stopwatch mode, etc. The display section 9 includes a day/mode name display W/M that displays the day of the week or mode name in two alphanumeric characters, and a digital display DH alarm 1 that displays the time or date in a 6-digit day-shaped segment. ~4 and mode display body AM ₁ ~ AM ₄ , DA, etc. to indicate date alarm mode.
PM mark, 24H mark, and SET mark display bodies are provided. Further, the switches _S1 to _S4 are push button type switches, _S1 is a mode changeover switch, and the other switches _S2 to _S4 are switches that perform predetermined functions in each mode.

FIG. 3 shows the configuration of RAM8. Here, one address of the RAM 8 has a storage capacity of 4 bits, and each row has an address structure of 8 columns. Then, in the first row of RAM8, AM/PM~1/
Current time data up to 256 seconds is stored. Second
The stopwatch time from 10 minutes to 1/256 sec and the contents of the second frequency dividing circuit 3 (1/16 sec,
1/256sec) is stored. The 3rd to 6th rows date store the alarm 1 to 4 setting times of the hour to 1 minute, and the 7th row stores the date of the date alarm. Also, P
is a 4-bit mode counter, Q is a 4-bit modification mode counter, and DRF is a 1-bit flag specifying the direct return function. Here, when the content of the mode counter P is "0", it is the basic clock mode, when it is "1", it is the alarm 1 mode, when it is "2", it is the alarm 2 mode, and when it is "3", it is the alarm 1 mode.
When the value is , the alarm 3 mode is specified, when the value is ``4'', the alarm 4 mode is specified, when the value is ``5'', the date alarm mode is specified, and when the value is ``6'', the stop watch mode is specified. Further, when the content of the mode counter P is "0" and the content of the correction mode counter Q is "1", the time correction mode is designated.

[Operation of the embodiment]

First, an overview of the overall operation will be explained according to the general flow shown in FIG. First, second
When the signal a is output from the frequency dividing circuit 3 of the input unit 7, a request is made for time measurement processing or for key input processing. (step _T1 ). Now, when key operation b is output from the input section 7 and input to the timing generator 4 and address section 5 to specify the key processing program corresponding to the operation key of the ROM 6,
_S1 processing (step _T2 ), _S2 according to the operation switch
Processing (Step T ₃ ), S ₃ Processing (Step T ₄ ), S ₄
Processing (step _T5 ) is executed. Here, if switches _S2 to _S4 other than display changeover switch _S1 are operated, the direct return designation flag DRF is set to "1" and the next operation of display changeover switch _S1 returns the A return to clock mode is specified (steps _T6 to _T8 ).

Next, the signal a is output from the second frequency dividing circuit 3 and input to the timing generator 4 and the address section 5 to designate the timekeeping processing program in the ROM 6, and the timekeeping processing is started (step 1).
_T9 ). In this timekeeping process, the contents of the second frequency dividing circuit 3 are written to a predetermined storage area of the RAM 8, and then the contents of the second frequency dividing circuit 3 are cleared. and,
Add the contents of the second frequency dividing circuit 3 written to RAM8 (1/16sec, 1/256sec) and the current time data in RAM8 (1/16sec, 1/256sec),
As a result, when a carry appears, the address in ROM 6 is changed and digit processing is executed. As a result of executing the above-described time measurement process every time the signal a is output in this manner, the current time data in the RAM 8 is updated. When the timekeeping process is completed, a match is detected between the current time and the set times of alarms 1 to 4 preset in RAM 8, and between the current date (not shown) in RAM 8 and the date of the preset date alarm. (Step T ₁₀ ). Here, if any match is detected, the buzzer drive circuit 14 is driven and an alarm sound is generated (step _T11 ). Furthermore, when no match is detected, display processing according to the setting mode is executed. That is, in the basic watch mode where the value of the mode counter P is "0", if the value of the correction mode counter Q is "1", this is detected in step _T12 and the correction display processing (step T12) is performed.
_T13 ) is performed, but if the value of the correction mode counter Q is "0", the basic clock display processing (step
T ₁₄ ) is performed. Also, when the value of mode counter P is "1", alarm 1 display processing (step
T ₁₅ ), "2" displays alarm 2 display processing (step
T ₁₆ ), "3" to display alarm 3 (step
T ₁₇ ), “4” displays alarm 4 (step
_T18 ), date alarm display processing (step _T19 ) is performed at "5", and stopwatch display processing (step _T20 ) is performed at "6".

Note that after the completion of such processing, the operation of the timing generator ₄ is stopped by the signal C1 from the operation decoder 13, and step _T1 is started.
It returns to the standby state again until there is a request for key input processing or time measurement processing.

Next, referring to FIG. 5, step T ₂ (S ₁
The specific contents of the processing) will be explained in detail. First, when entering this _S1 process, the setting mode is determined according to the value of the mode counter P (step
_T31 ). That is, step _T31 is to determine whether the mode is in alarm 1-4 mode according to the value of the mode counter P being "1" to "4", and if the value of the mode counter P is "0", that is, For example, when the mode changeover switch _S1 is operated in the basic clock mode in which the current time _etc. are displayed as shown in FIG. will be judged.
This flag can be set using the display switch according to the flow shown in Figure 4.
It is set to "1" when a switch other than _S1 is operated. Here, the flag DRF is “0”
Assuming that, at the next step _T33 , it is determined that the value of the mode counter P is "6", that is, the stopwatch mode, but since the mode is now the basic watch mode, the process advances to step _T34 . Here, an increment process is executed to increment the value of the mode counter P by 1, whereby the value of the mode counter P changes from "0" to "1", and the alarm 1 mode is set. Next, in step _T35 , the same process as in step _T33 described above is executed, but since the value of the mode counter P is now "1", an alarm mode display process (step _T36 ) is carried out, The mode name (AL1) is displayed as shown in FIG. 6B. Then, in the next step _T37 , it is determined whether the basic clock mode has changed to the alarm 1 mode depending on whether the value of the mode counter P is "1" or not. Since the value of the mode counter P is now "1", the direct return designation flag DRF is cleared in the next step _T38 , but if it is other than "1", such clearing processing will not be executed. After clearing the value of the correction mode counter Q, an operation sound accompanying the operation of the switch _S1 is generated (steps _T39 and _T40 ).

When the alarm time is preset in the alarm 1 mode, the switch operation procedure shown in FIG. 6 is performed. That is, when the switch _S2 is operated, first, the hour digit is selected and the SET mark lights up, indicating that the alarm setting mode is in effect (see FIG. 6, B1). In this state, the hour digit is incremented by -1 according to the number of times switch _S3 is operated, and by +1 according to the number of times switch _S4 is operated.
This makes it possible to set the alarm time in desired units of hours. Next, by operating switch S ₂ once, the minute digit will be selected (see Figure 6, B2).
reference). Therefore, similarly to the above, switches S ₃ and S ₄
When the desired value is set in the minute digit by the operation , and then the switch S ₂ is operated again, the display returns to the display state shown in FIG. 6B. When the desired alarm time is set in this way, the flag DRF is set to "1" in the flow shown in Figure 4.
is set to .

In this alarm 1 mode, when the mode changeover switch _S2 is operated, the _S1 process in _{FIG .}
Then, the value of mode counter P becomes "2".
Therefore, the alarm 2 mode is set. Therefore, in alarm 1 mode, regardless of whether the direct return designation flag DRF is "1", the next alarm 2 is executed without returning to the basic clock mode.
It will move to mode. This causes the alarm 2 mode name (AL2) to be displayed (see Figure 6C).
After clearing the correction mode counter Q, a notification tone is generated (steps T ₃₆ , T ₃₉ , T ₄₀ ). After setting the alarm 2 mode in this manner, a desired alarm time is set according to the same key operation procedure as described above.

Next, in this alarm 2 mode, when the mode changeover switch S ₁ is operated, the same S ₁ process as described above is executed, and as a result, the alarm 3 mode is set, and the mode name is as shown in Figure 3D. Is displayed. Next, in this alarm 3 mode,
When mode selector switch S ₁ is operated, alarm 4
mode, and the displayed content at this time is 3rd mode.
When the mode changeover switch _S1 is further operated, the date alarm mode is set, and the display contents at this time are as shown in FIG. 6F. Therefore, in the alarms 1 to 4 modes, each time the mode changeover switch _S1 is operated, the mode is sequentially shifted to the next mode, and the direct return function does not work.

In the date alarm mode, the value of the mode counter P is set to "5", so when the _S1 process is entered by operating the mode changeover switch _S1 , the process proceeds from step _T31 to _T32 , and direct return is performed. Branches depending on whether the designated flag DRF is "0" or not, and if it is "1", that is, if a switch other than switch _S1 has been operated, the step branches.
_T41 to _T43 are executed sequentially, and the mode counter P,
Direct return designation flag DFR and modification mode counter Q are cleared. Then, the process proceeds to step _T40 , where an operation sound is generated. Therefore, when the mode changeover switch _S1 is operated in the date alarm mode, the switch _S1 is operated in the alarm 1 to 4 modes and the date alarm mode.
If a switch other than the above is operated, that is, if the direct return designation flag DRF is set to "1", the value of the mode counter P is set to "0" to return to the basic clock mode. Become. On the other hand, in date alarm mode, the direct return designation flag DRF is “0”
In this case, this is detected in step _T32 , and the process proceeds to step _T34 via step _T33 , where the value of the mode counter P becomes "6" and the stop watch mode is set. As a result of incrementing the value of the mode counter P in this way, when the stop watch mode is established, the process proceeds from step _T35 to step _T44 , where the value of the correction counter Q is cleared. Then, the process proceeds to step _T40 , where an operation sound is generated.

The initial display state in this stop watch mode is as shown in FIG. 6G, and in this state, when switch _S4 is operated, the start/stop operation is controlled. When the mode changeover switch _S1 is operated in the stopwatch mode, if the flag DRF is "1" and the direct return function is specified, as in the date alarm mode described above, steps _T41 to T are performed. ₄₃
As a result of being executed sequentially, the mode returns to the basic watch mode, but if it is "0", the process proceeds to step _T33 , where it is determined that the stopwatch mode is in effect, and steps _T45 to _T47 are executed sequentially. By this,
The value of the mode counter P is cleared, and then the flag DRF is set to "1", and then the correction counter Q is set to "1". Then, the process proceeds to step _T40 , where an operation sound is generated. Therefore, by executing steps _T45 to _T47 , the basic clock correction mode is entered. FIG. 6H shows the display state in this case. In this correction mode, switch _S2 is a digit selection switch, _S3 is a -1 step switch, and _S4 is a +1 step switch, and the time and date can be corrected by operating these switches. When the mode changeover switch _S1 is operated in this basic clock correction mode, the flag DRF is set to "1", so steps _T41 to _T43 are executed to return to the basic clock mode. Become.

In this way, in this embodiment, alarms 1 to
Even if flag DRF is "1" when in 4 mode, the next operation of switch _S1 will not return to basic clock mode, but flag DRF will be "1" when in date alarm or stopwatch mode. If so, the next switch _S1 will return to the basic clock mode.

It should be noted that this invention is not limited to the above-mentioned embodiments, and can be modified and applied in various ways without departing from the invention.For example, it goes without saying that the types and number of modes are not limited to the above-mentioned embodiments.

[Effect of idea]

As explained above, this invention includes a mode storage means for storing the displayed mode and two or more modes stored in the mode storage means, such as an alarm mode, and which are continuous. mode detecting means for detecting whether or not the mode is in a predetermined mode which may be switched and displayed and further controlled continuously by switch operation, and when in the predetermined mode, the functions of other switches other than the display changeover switch are If the function is running, operating the display changeover switch will return to the basic clock mode, and if no other switch function is being executed, operating the display changeover switch will move to the next mode, while returning to the above specified mode. In some cases, when the display changeover switch is operated, regardless of the execution of other switch functions,
Since the mode is moved to the next mode, the direct return function can be operated according to the mode, and the single mode changeover switch can be used to efficiently change the mode.

[Brief explanation of the drawing]

The drawings show one embodiment of this invention; Fig. 1 is a block circuit diagram of an electronic watch, Fig. 2 is a diagram explaining the structure of the display section and types of switches, and Fig. 3 is a diagram illustrating the structure of the display section and the types of switches.
A diagram showing the configuration of a part of the RAM, FIG. 4 is a diagram showing a flowchart explaining the overall operation,
FIG. 5 is a flowchart illustrating the specific contents of the _S1 process shown in FIG. 4, and FIG. 6 is a diagram of display states that change in response to switch operations. 1...Oscillation circuit, 2...First frequency dividing circuit, 3...
... Second frequency divider circuit, 4 ... Timing generator, 5 ... Address section, 6 ... ROM, 7 ... Input section, 8 ... RAM, 11 ... Arithmetic section, 13 ...
Operation decoder, S ₁ ... mode changeover switch, S ₂ , S ₃ , S ₄ ... switch.

Claims (1)

[Claims for Utility Model Registration] An electronic timepiece comprising mode control means for sequentially switching and displaying a basic timepiece mode and a plurality of other function modes in a predetermined order each time a single display changeover switch is operated, comprising: The means includes a mode storage means for storing the displayed mode, and a means for detecting whether the mode stored in the mode storage means is one of two or more consecutive predetermined modes among the plurality of other function modes. mode detection means; when the mode detection means detects that a mode other than the predetermined mode is stored in the mode storage means and the display changeover switch is operated, a mode other than the display changeover switch is activated; a first mode control means that determines whether or not another switch function has been executed, and switches to the basic clock mode when the function is executed, and switches to the next mode when it is not executed; and the mode detection means. When the display changeover switch is operated while it is detected that the predetermined mode is stored in the mode storage means,
An electronic timepiece characterized by comprising: second mode control means for switching to the next mode regardless of the execution of the functions of the other switches.