JPS634675B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for an electronic timepiece, and more particularly to a switch circuit for a CPU type electronic timepiece using a 4-bit microcomputer.

In general, CPU-based electronic clocks have the advantage that when specifications change, multiple functions can be realized much more easily by simply changing the mask of the ROM that stores the program, compared to the conventional frequency-dividing method based on a counter configuration. However, conventional CPU-based electronic watches perform addition processing by counting the number of program steps based on the processing time of one instruction, resulting in long and complicated programs. Furthermore, since it operates constantly at high speed, it has the drawback of increasing current consumption and shortening battery life, making it unsuitable for clocks, wristwatches, etc. that use batteries as a power source. In addition, the functions of externally connected switches are fixedly determined by AND-ORROM, etc., and functions cannot be set or added by a program, which is inconvenient and restricts when specifications are changed. .

The present invention has been made in view of the above-mentioned points, and it performs clock operations etc. using interrupt processing, and stops the operation of the CPU except when necessary, at least in the case of interrupt processing by switch operation and when specified by a program. The present invention provides an electronic clock that is easy to program and consumes little current by restarting the operation of the CPU when a switch operation is performed. The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, which includes a reference signal generation circuit 1, a clock generator 2, a switch input circuit 3, a state control circuit 4, a timer counter 5, a chronograph counter 6,
ROM7, program counter 8, stack 9,
Instruction register 10, control circuit 1
1. Consists of ALU 12, ACC 13, RAM 14, decoder 15 and latch circuit 16
It is a CPU-type electronic clock.

A reference signal generation circuit 1 oscillates a signal with a frequency determined by a crystal oscillator 17 connected to an external terminal, further divides the signal, and sends a predetermined frequency-divided signal to a clock generator 2 and a switch input. circuit 3,
Timer counter 5 and chronograph counter 6
etc. Further, the reference frequency generating circuit 1 outputs an interrupt signal INT2 for causing a time counting operation to be performed at fixed intervals, for example, every 0.5 seconds.

The clock generator 2 generates a clock signal for operating the CPU based on the frequency-divided signal applied from the reference frequency generating circuit 1, and supplies it to each section. A stop signal CLKSTOP for stopping the clock signal generation operation is applied from the state control circuit 4 to the clock generator 2, and interrupt signals INT0, 1, 2, 3 and a timer are output.
TIMEROUT and operation start signal
CLKSTART is applied and these signals restart the stopped operation.

Switch input circuit 3 has external terminals M ₁ to _{M 4} and S ₁
~ _S4 , which prevents the switches connected to each external terminal from chattering and captures switch opening/closing data, and the data is sent to the respective data buses DB. Especially external terminals S ₁ ~ _{S 4}
The opening/closing of the switch connected to can be specified by the switch control signal SWCON of the state control circuit 3, and the operation start signal CLKSTART can be output depending on the opening/closing of the specified switch. Further, an interrupt signal INT3 can be output by closing a switch connected to external terminals _S1 to _S4 .
In addition, in chronograph mode, terminals S ₁ and S ₂
A chronograph control signal CHRCON is output that controls the start, lap, and stop of the chronograph counter 6 by opening and closing a switch connected to the chronograph counter 6.

State control circuit 4 is instruction bus IB
It controls the state of each circuit in various modes, and controls the switch control signal SWCON that controls the switch input circuit 3, the reset and start of the timer counter 5, and the timer time. Timer control signal TIMCON for making selections, etc. and stop signal for stopping the operation of clock generator 2
Output CLKSTOP etc. Furthermore, an external terminal LAMP for connecting a lamp and an external terminal ALM for connecting to an alarm sound generator are provided.

Timer counter 5 is the instruction bus
The timer time can be set according to the program sent to the IB, and when the timer time elapses, a signal TIMEROUT is output to start the operation of the clock generator 2. The chronograph counter 6 is a counter that counts pulses of 1/100 seconds, and outputs an interrupt signal INT1 every 1/10 seconds. In addition, the count contents of the chronograph counter 6 are sent to the decoder 15 via the chronograph data bus CDB.
is applied to

The ROM 7 consists of 1392 x 14 bits, in which programs for timekeeping operations and control of various parts are written in a fixed manner. An instruction code consisting of the following is output to the instruction register 10. The instruction register 10 stores the instruction code output from the ROM 7 and is connected to the instruction bus.
Output to IB. After processing one instruction, the program counter 8 receives the next address or jump control signal and outputs the jump destination address signal.
Output to ROM7. The stack 9 has a capacity of 8 levels, and when transitioning to an interrupt process or subroutine, the contents of the program counter 8 are set to 1.
The added value is memorized. However, after the instruction "SCP" to stop the operation of the clock generator 2 is executed, when interrupt processing is performed, the contents of the program counter 8 are stored as they are in the stack 9, and after the interrupt processing is completed, the clock is restarted. The stop command “SCP” is addressed and executed.

The RAM 14 consists of 84×4 bits, and data such as current time, alarm time, timer time, etc. is stored in a predetermined area. The address of the RAM 14 is specified by an instruction, and the data stored at the specified address is sent to the data bus DB, or the data sent to the data bus DB is specified by a send command or a write command. The address is saved. The ALU 12 inputs the data sent to the data bus DB, performs processing such as addition and subtraction, stores the results in the ACC 13, and sends the data to the data bus DB again.

The decoder 15 and the latch circuit 16 constitute a display circuit, and the decoder 15 converts the applied 4-bit data into 7 segment signals for display and outputs them to the segment bus SB. Latch circuit 1
Reference numeral 6 stores and holds the segment signals output to the segment bus SB and outputs them to external terminals a to g, and there are as many as the number of display elements. Which latch circuit 16 is to store the converted segment signal is specified by the program. For example, when converting the data of the first digit of the second of the current time, the latch circuit 16 stores the converted segment signal. The latch circuit 16 corresponding to the display element on which the digit is to be displayed is specified by the program. On the other hand, in addition to the data bus DB, the output chronograph data bus CDB from the chronograph counter 6 is applied to the decoder 15, and either the data bus DB or the chronograph data bus CDB can be switched and selected depending on the program.

The control circuit 11 decodes the instructions from the ROM 7 sent to the instruction bus IB and controls each circuit using the timing signal output from the clock generator 2 in order to perform the operation corresponding to the instruction. Yes, plus interrupt signal INT
When 0, 1, 2, or 3 is output, the program counter 8 and
Controls ROM7.

Figure 2 shows the switch input circuit 3 shown in Figure 1.
FIG. The external terminals S ₁ -S ₄ are connected to input circuits 18 - 21 having exactly the same circuit configuration, respectively, and the switches SW ₁ -SW ₄ are connected to the external terminals S ₁ -S ₄ . The input circuits 18 to 21 each include a chattering prevention circuit 22, a NOR gate 23, latch circuits 24 and 25, an inverter 26, and a NOR gate 2.
It consists of 7 and 28. The chattering prevention circuit 22 receives the divided output φ1 from the reference signal generation circuit 1 applied via the NAND gates 29 and 30.
0, removes the chattering that occurs when switches SW ₁ to _{SW 4} open and close, and sends the signal to NOR gate 2.
3 and also to each NAND gate 31. The output of a D-FF (D type flip-flop) 32 to which the output of the NAND gate 31 is applied is applied to a NOR gate 23, and the signals of each chattering prevention circuit 22 are delayed and outputted from the NOR gate 23. The output of NOR gate 23 is connected via transmission gate 33 to each bit DB0, DB1, DB2 and DB3 of data bus DB. Latch circuit 24 and NOR gate 27
operates when switches SW ₁ to SW ₄ are closed,
The latch circuit 25 and the NOR gate 28 operate when the switches SW ₁ to _{SW 4} are opened, but this operation is controlled by the switch operation designation signal from the state control circuit 4 applied to the reset terminal R of the latch circuits 24 and 25. ₁ to ₄ and ₁ to ₄ . In addition, the latch circuits 24 and 25 have NAND
A frequency-divided output φ10 is applied via gates 29 and 30. Each output of NOR gates 27 and 28 is NOR
The output of the NOR gate 34 is applied to the NAND gate 29 and the divided output φ1 is applied to the gate 34.
0 and is applied to the clock generator 2 via the inverter 35 as the operation start signal CLKSTART.

On the other hand, the interrupt generation circuit 36 switches SW ₁ to
When any of SW ₄ is closed, if the interrupt signal output is possible, it is set, and the output is sent to the NAND gate 38 and NOR via the inverter 37.
FF (flip-flop) 3 that controls the gate 23
9, a latch circuit 40 and a NOR gate 41 that cut out the signal output from the NAND gate 38,
The interrupt signal INT is set by the output of the NOR gate 41 to remember that it is an interrupt request.
It is composed of an FF 42 that outputs 3, and an FF 43 that stores the state in which interrupt signal output is enabled and whether output of switch data is prohibited.

Next, the operation of the circuit shown in FIG. 2 will be explained.
First, when the output of the NOR gate 34 is "1", the operation start signal CLKSTART is "0" and does not instruct the clock generator 2 to start operating.
In addition, when the switch data hold release signal - is "1", the frequency divided output φ10 is output from the NAND gate 2.
9 and 30, and the latch circuits 24 and 2
A clock is supplied to the clock terminals φ of 5, 40 and D-FF 32. On the other hand, interrupt generation circuit 3
6 is not in the set state, the output "0" of the inverter 37 is applied to the NOR gate 23. So, for example, switch SW ₁ is closed and external terminal S ₁ is connected.
When the V _DD level, that is, "1" is applied, the output of the chattering prevention circuit 22 changes from "1" to "0", and the output of the NAND gate 31 becomes "1".
The D-FF 32 is inverted one cycle after the frequency division output φ10 and applies an output “0” to the NOR gate 23.
The NOR gate 23 becomes conductive due to the output becoming "0" and outputs a signal " ₁ " indicating that the switch SW1 is closed. At this time, when the switch operation designation signal ₁ applied to the reset terminal R of the latch circuit 24 is "1", that is, the switch SW ₁
When the closing of latch circuit 2 is not specified,
4 remains reset and NOR gate 27
The output of is "0". Furthermore, even if the switch operation designation signal ₁ of the latch circuit 25 is "0", the latch circuit 25 and the NOR gate 28 operate at the falling edge of the input signal, so the output of the NOR gate 28 is "0" at this time. It is. Therefore, the output of the NOR gate 34 remains at "1" and the operation start signal CLKSTART is not output.
On the other hand, when the switch operation designation signal ₁ is "0", the NOR gate 23
Since the output of the latch circuit 24 to which the inverted signal of the output of is applied is "0", the NOR gate 2
7 outputs "1". Therefore, the output of the NOR gate 34 becomes "0", and the operation start signal is
CLKSTAT "1" is output, and if the operation of the clock generator 2 has stopped, the operation is restarted. Furthermore, the output “0” of the NOR gate 34 is
Since the divided output φ10 is cut off at the NAND gate 29, the chattering prevention circuit 22, D-
The operation of the FF 32 and the latch circuits 24 and 25 is stopped, and the same state, that is, the switch data is maintained. When the clock generator 2 starts operating, the program in the ROM 7 shown in FIG. 1 advances, and when the switch data input command in the program is executed, the transmission gate 33
is opened and the switch data is sent to the data bus DB.

Signal to release switch data retention
When a pulse that becomes “0” is output to RESET
The output of the NAND gate 30 becomes "1". This signal causes the latch circuit 24 to invert and set the signal to "1", so the output of the NOR gate 27 becomes "0".
Therefore, the output of the NOR gate 34 becomes "1" and the operation start signal CLKSTART becomes "0".
The NAND gate 29 passes the divided output φ10.

When switch SW ₁ is opened, the output of the chattering prevention circuit 22 changes from “0” to “1”, and the output of the NOR gate 23 changes from “1” to “0”.
becomes. As mentioned above, if the switch operation designation signal ₁ "0" is applied to the latch circuit 25, the output of the NOR gate 28 becomes "1", the operation start signal CLKSTART "1" is outputted, and the switch data is held. .

In this way, the switch designation signals ₁ to ₄ and
By selecting S ₁ -S ₄ DOWN, the designation of the switch operation can be set, and the operation of the clock generator 2 can be started when the designated switch operation is performed. For the switch designation signals ₁ to ₄ and ₁ to ₄ , the outputs of FFs (flip-flops) provided in the state control circuit 4 for the number of signals are used, and the FFs are used to execute the switch operation designation command, for example, the instruction code thereof. If it is 110000XXXXXXXX, it is set based on the data of the lower 8 bits.

On the other hand, interrupt processing can also be performed by closing any one of the switches _SW1 to _SW4 . That is, when an instruction for setting an interrupt is executed, a pulse of "0" is generated in the interrupt set signal. FF43 is set by this signal and becomes its output, and NOR gate 4
The output of 4 becomes "1". FF to which “1” is applied
39 is set and the output of the inverter 37 is "1"
and makes the NAND gate 38 conductive.
Block NOR gate 23. If any of switches SW ₁ to _{SW 4} is closed in this state, NAND
The output of the gate 31 becomes "1", but the output of the chattering prevention circuit 22 is not output from the NOR gate 23. The output of NAND gate 31 is “1”
As a result, the output of the NAND gate 38 becomes “0” and the latch circuit 40 and the NOR gate 41
cuts out the falling edge and applies a pulse of "1" to the FF42. The FF 42 is set by this pulse and outputs, ie, interrupt signal 3, to "0". The operation of the clock generator 2 is restarted in response to the interrupt signal 3 "0", and predetermined interrupt processing is performed. Also, when an interrupt is accepted, the reset signal INT3RESET becomes “1”.
A pulse is generated and the latch circuit 40 and FF 42,
43 is reset. On the other hand, FF39 is reset when switches SW ₁ to _{SW 4} are opened.
This is done when the output of the NOR gate 45 to which the output Q of 32 and the output of the NAND gate 31 are applied becomes "1".

The interrupt generation circuit 36 can also forcibly issue an interrupt depending on a command. When the interrupt request instruction is executed, interrupt request signal 3REQ "0" is output, FF42 is set via inverter 46, and interrupt signal 3 "0" is output.
output. On the other hand, if the interrupt generation circuit 36 is in the set state, the FFs 43 and 39 are reset.
This interrupt request command is executed, for example, when a mode change or the like is performed while an alarm is sounding, and it is used to forcibly interrupt and stop the alarm sound.

3 and 4 are flowcharts showing examples of programs written to the ROM 7, with FIG. 3 showing a main program and FIG. 4 showing an interrupt processing program. 1 with reference to Figures 3 and 4.
The overall operation of the block diagram shown in the figure will be explained.

First, when power is applied, initial clear is activated, each circuit is reset, and the program counter 8 is reset.
specifies address 0 of ROM7. Starting from address 0, a program for initial settings is written.
By executing this program, "0" or predetermined data is stored in the RAM 14 and initial settings are made. Next, a mode change program is executed. This program is switch input circuit 3
Data indicating whether the switch is open or closed is transferred from the data bus.
Input via DB and determine whether current time mode, alarm mode, timer mode, chronograph mode, or other modes are selected depending on the content of the data. , RAM1 corresponding to each mode
Set the flags in 4. Then, a predetermined address of the ROM 7 in which the selected program is written is specified, and the program jumps there.
In this embodiment, mode selection is performed using external terminals M ₁ to _{M 4} and
switch connected to S ₄ (each
MS ₁ to MS ₄ and SW ₄ ), and switches connected to external terminals S ₁ to _{S 3} (these switches are SW ₁ to _{SW 3} ) are used to execute corrections, turn on the lamp, and stop the alarm sound. It is programmed to do this. However, by changing the program, it is possible to use two to four arbitrary switches to select a mode or perform other operations. Furthermore, when the mode is changed, if an alarm is being sounded, an interrupt request signal INT3REQ is output, and the alarm sound is stopped according to the interrupt processing INT3.

In the current time mode, the current time is first displayed. This is done by sequentially addressing the seconds, minutes, hours, month, day, day, etc. stored in each digit at a predetermined address in the RAM 14 using a display command that can specify addresses in the RAM 14, and transmitting the data to the data bus.
The segment signal converted by the decoder 15 is stored in the latch circuit 16 to be displayed. At this time, the decoder 15 has a data bus in advance.
Control with commands so that the DB is connected. In particular, in the case of hour display, it is determined whether 12-hour display or 24-hour display is selected, processing is performed that suits the display, and the result is sent to the decoder 15.
is applied and displayed. On the other hand, in the case of displaying the day of the week, the function of the decoder 15 is switched by a command for converting the day of the week, and then data on the day of the week is applied. Latch circuit 16
is the stored segment signal until the next new segment data is rewritten to the external terminals a to g.
Since the clock generator 2 continues to be outputted, the display will continue even if the clock generator 2 stops operating.

After the display is performed as described above, RAM1
4, which indicates whether the mode is in correction mode or not, and if it is in normal display mode, the switch is turned on.
Close SW ₁ , switch SW _{1 to 3} if in correction mode
Set the closure of That is, in response to the execution of this command, the state control circuit 4 outputs the switch control signal SWCON and controls the switch input circuit 3 to perform the specified operation of the specified switch, that is, to close switch SW _{1 or to switch SW 1} to SW _3. Control is performed so that the operation start signal CLKSTART is output only when the closing is performed. When the switch settings are completed, a command "SCP" for stopping the operation of the clock generator 2 is executed. When this instruction code is sent to the instruction bus IB and applied to the state control circuit 4, the state control circuit 4 sends a stop signal.
Output CLKSTOP and clock generator 2
Set the flip-flop inside. By setting this flip-flop, the divided signal from the reference signal generating circuit 1 is cut off, and generation of the system clock is stopped. Therefore, the execution of the program does not proceed to the next step with the stop command "SCP", and all operations based on the program are stopped. Therefore, during this time, the current flowing through the system is drastically reduced.

The clock generator 2 starts operating again when a specified switch is operated, when an interrupt request INT0, 1, 2, or 3 is received, or when the timer counter 5 counts up. , the flip-flops of clock generator 2 are reset by these signals. In the case of an interrupt, the clock generator 2 starts operating, but the contents of the program counter 8, that is, the contents addressing the stop instruction "SCP", are saved to the stack 9, and the interrupt processing program shown in FIG. The address indicated is set in the program counter 8. When the interrupt processing is completed, the address saved in stack 9 is set in program counter 8, so the stop command "SCP" is issued again.
is executed and the operation stops. On the other hand, when the specified switch is operated, the switch input circuit 3 outputs an operation start signal CLKSTART, and when the timer counter 5 counts up, it outputs a timer output TIMEROUT. These outputs reset the flip-flop of clock generator 2 to resume operation and the program proceeds to the next step.

The next program checks the mode change flag in the RAM 14 and determines whether there is a mode change request. If a mode change is requested, the program jumps to the mode change program described above, and if there is no request, the program proceeds to the next program. The mode change flag is set or reset by interrupt processing INT0. INT0 will be described later, but it is a switch for selecting the mode MS ₁ to _{MS 4}
The status of SW ₄ is periodically checked, and if the mode is changed, the flag is set to "1" and the timer counter 5 is started. Therefore, when a mode change is requested, the timer output TIMEROUT is used to operate the clock generator 2 to perform the mode change.

On the other hand, if there is no mode change request, it means that the specified switch has been operated, and the next program will determine whether it is in the correction mode or not and which of switches SW ₁ to _{SW 3} has been closed. It makes a judgment and performs the processing corresponding to the operation. For example, when switch SW ₁ is closed in normal mode, a command to turn on the lamp is executed, the external terminal LAMP of state control circuit 4 is set to "1", and the next command turns on the switch.
Specify SW ₁ open and clock stop command “SCP”
Execute. When the switch _SW1 is opened, the operation starts again as described above, the command to turn off the lamp is executed, and the program jumps to the switch setting program again. Also, in the correction mode, switch
When SW ₁ is closed, the second data stored in the RAM 14 is rewritten to "0". At this time
Determine whether it is 29 seconds or 30 seconds, and if it is 30 seconds or more, perform digit stop processing. When switch SW ₂ or SW ₃ is closed, the hour or minute in RAM 14 is
It is transferred to the ALU 12, incremented by 1, and written to the RAM 14 again. Furthermore, if switch SW ₂ or SW ₃ continues to be closed, fast-forward correction is performed. In this case as well, the switch operation is designated and the clock operation stop command "SCP" is used. That is, the timer counter 5 is set to 1 second and started, and after specifying the opening of switches SW ₂ and SW ₃ , the stop command "SCP" is executed. Therefore, clock generator 2 starts operating when switch SW ₂ or
When SW ₃ is opened and timer counter 5 is 1
This is a case where seconds are counted, and by determining switch SW ₂ or SW ₃ in the program after the operation starts, it can be determined whether it has been closed for a certain period of time. After adding 1 to , it sets 250 ms to timer counter 5 and jumps to the program that specifies opening of switches SW ₂ and SW ₃ again. As a result, the values are added and fast-forwarded every 250 ms until switch SW ₂ or SW ₃ is opened. In this modification program, when the seconds are reset and the minutes or hours are added, the data modified by the display command is immediately sent to the data bus DB and displayed.
When switches SW ₂ and SW ₃ are opened, the program jumps from the modification program to the switch setting program described above.

Alarm mode, timer mode, and chronograph mode are also programmed in the same pattern as the current time mode described above.

When in alarm mode, depending on the display command
The data at the address where the alarm time is stored in the RAM 14 is sequentially designated and displayed digit by digit. The switch can be specified in alarm setting mode.
Specify the closing of SW ₁ to ₃ , specify the closing of switch SW ₁ in alarm display mode, and execute the operation stop command “SCP”. If there is no mode change request and the specified switch is closed, the program proceeds to alarm time setting, display and lamp blinking programs. In the alarm mode, when switch SW ₁ is closed, the lamp lighting command, switch SW ₁ open designation, and operation stop command "SCP" are executed even in the alarm setting mode, and after the operation starts, the lamp extinguishing command is executed. Depending on the situation, the lamp is turned on and off. On the other hand, when the switch SW ₂ or SW ₃ is closed, the mode is the alarm time setting mode, and the minute or hour of the alarm time is set. This program uses the same program as the current time correction program, and uses the addition process as a subroutine to memorize the hour or minute of the alarm time.
Program it to specify the address of RAM14. Of course, the set contents are immediately displayed by a display command.

In the timer mode, the timer time display program, switch setting program, and operation stop command "SCP" are similarly executed in sequence. In this case, the timer is not timer counter 5, but RAM
It is a timer with seconds, minutes, and hours stored in 14. The display command therefore addresses a timer in RAM 14. In the timer mode, there is no correction mode, and when setting the switch, it is determined whether or not to generate an alarm sound, and when the alarm sound is to be generated, switches SW ₁ to _{SW 3} are set to close.
When not generating an alarm sound, only set switch SW ₁ to close. If the operation resumes and there is no mode change, the program will set the timer time,
Proceed to display, start, stop and lamp flashing programs. If the mode does not generate an alarm sound when the switch SW ₁ is closed, the lamp is turned on and off using the lamp blinking program in the same way as in the current time mode and alarm mode. On the other hand, switch SW ₂ or
Once SW ₃ is closed, it will be modified depending on the minute or hour and modification program. Also, when switch SW ₁ is closed in a mode that generates an alarm sound, a flag for starting the timer is set in the RAM 14 if the timer is set, and nothing is done if the timer is not set. Jump to the switch setting without doing so.

The chronograph display in chronograph mode is
1/10 second of the chronograph time in RAM14, second,
The minutes and hours are displayed sequentially using the display command, and the data bus
1/100 of the chronograph counter 6 by switching the chronograph data bus CDB to the decoder 15 with a switching command between DB and chronograph data bus CDB.
Second data is displayed. Directly applying 1/100 second data to the decoder 15 in this way would require a program to display each digit, which would take a long processing time and would not be able to track 1/100 second data, resulting in accurate data. This is because it cannot be displayed.

In the switch setting, switches SW ₁ and ₂ are set to close. When switch SW ₁ or ₂ is closed, the operation starts and the program proceeds, but in the case of chronograph mode, the chronograph control signal is sent from switch input circuit 3 regardless of the program.
CHRCON is output and controls the chronograph counter 6. That is, the flip-flop that controls start and stop in the chronograph counter 6 is set or reset by the chronograph control signal CHRCON output when switch SW ₁ is closed, and the chronograph control signal CHRCON is output when switch SW ₂ is closed. Signal CHRCON sets or resets the flip-flop for the lap flag to display 1/100 second laps.

On the other hand, the program checks the control flip-flop and wrap flag flip-flop in the chronograph counter 6 to determine whether the chronograph counter 6 has started or is in a wrap state, and checks the chrono stop flag and wrap flag in the RAM 14. Set or reset. Further, when the switch SW ₂ is closed while the chronograph counter 6 is in the stopped state and the wrap flag is set, the chronograph data in the RAM 14 is reset. At the end of this program, the chronograph data in the RAM 14 is displayed using a display command, and a jump is made to the switch settings.
Incidentally, addition processing is performed on the chronograph data in the RAM 14 according to the interrupt signal INT1 output from the chronograph counter 6 every 1/10 seconds.

The interrupt processing INT0 shown in FIG. 3 takes a certain period of time, for example, every 62.5 ms, and samples the switches MS ₁ to MS ₄ and SW ₄ . That is, the data of the switches MS ₁ to MS ₄ and SW ₄ are inputted from the switch input circuit 3, stored in the RAM 14, and compared with the data sampled last time. If there is no change as a result, reset the mode change flag in RAM 14 and return to the main program; if there is a change, set the mode change flag and timer counter 5 to 32ms, start it, and return. do.

Interrupt processing INT1 takes place every 1/10 second when the chronograph counter 6 is started. This process adds 1 to the 1/10 second data of the chronograph data in RAM 14, and if there is a carry, it is carried to the chronograph second data, and if there is a carry, it is carried to the upper digit, and so on. . Next, if the chronograph mode is not in the lap state, the chronograph data is displayed using a display command and the process returns to the main program.

The interrupt processing INT2 is generated from the reference signal generation circuit 1 every 1/2 second, and performs timekeeping processing and the like. First, the data of the 1/2 second flag in the RAM 14 is taken into the ALU 12 and 1 is added to it, and it is determined whether the result is "1" or "2". If it is "1", it returns to the main program. “2”
In this case, set "0" to the 1/2 second flag and perform timer processing. Timer processing is executed only when the timer has started. If it has started, 1 is subtracted from the seconds of the timer data in RAM 14, and if there is a borrow, 1 is further added from the upper digit.
Perform borrow processing by subtracting . Also, as a result,
It is determined whether the seconds, minutes, and hours have all become "0", and if they are "0", an alarm sound command is executed and an alarm sound for the timer is output to the external terminal ALM.
Next, 1 is added to the second data of the current time, and if there is a carry, carry processing is performed. If there is a carry to the minute digit in this carry process, alarm processing and snooze processing are performed. In the alarm process, the hour and minute data stored in the RAM 14 and the hour and minute data of the current time after the carry process are extracted for each digit into the ALU 12 and it is determined whether they match. If they match, an alarm sound generation command and an interrupt INT3 set command are executed to enable an interrupt from the switch input circuit 3. Snooze processing determines whether there is a snooze request, and if there is a snooze request,
Add 1 to the snooze data in RAM14,
When the result reaches a predetermined time, for example, 5 minutes, the alarm sound generation command and interrupt INT3 set command are executed again. Next, it is determined whether the mode flag in the RAM 14 is the current time mode, and if the mode is the current time mode, the new, carried current time data is displayed, and if it is another mode, the process returns to the main program.

Interrupt processing INT3 is set to switch input circuit 3 when an alarm sound occurs, and switches SW ₁ to
Required when any SW ₄ is closed. This process stops the alarm signal output from the external terminal ALM of the state control circuit 4 with an alarm sound stop command, sets the snooze flag if there is a snooze request, sets the snooze data in the RAM 14, and returns. do. If there is no snooze request, the flashing of the alarm sound mark is stopped, the snooze flag is reset, and the process returns. If interrupt INT3 is set, even if any of SW ₁ to _{SW 4} for which a switch is specified is operated, only the interrupt signal INT3 will be output from the switch input circuit 3, and the switch specification will be ignored. Ru.

The priority order of interrupt processing is INT0, 1, 2,
3, which is determined by the control circuit 11. Also, interrupt signals INT0, 1,
2 and 3 are connected to set the flip-flops of the control circuit 11, respectively, and when interrupts are disabled, interrupt processing is performed after the inhibition is canceled. If these interrupt processing are requested while the system clock is stopped, the operation stop command "SCP" is executed again after the interrupt processing.

As described above, according to the present invention, interrupt processing and switch operation can be specified by closing the switch.
The clock generator can restart operation only when the specified switch is operated, and since the switch functions can be set by a program, there are no restrictions when changing specifications, making it highly versatile. An electronic clock is obtained, and power consumption is greatly reduced because the system stops operating except when necessary.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a partial circuit diagram of the switch input circuit shown in FIG. 1, and FIGS. 3 and 4 are flowcharts showing example programs. be. DESCRIPTION OF SYMBOLS 1... Reference signal generation circuit, 2... Clock generator, 3... Switch input circuit, 4... State control circuit, 5... Timer counter, 6... Chronograph counter, 7... ROM, 8... ...Program counter, 9...Stack, 10...Instruction register, 11...Control circuit, 12
...ALU, 13...ACC, 14...RAM, 1
5...Decoder, 16...Latch circuit.

Claims (1)

[Claims] 1. A reference signal generation circuit, a clock generator that generates a clock signal that controls the operation of the entire circuit based on the output of the reference signal generation circuit, and a switch input that receives open/close signals from multiple externally connected switches. A circuit, a ROM in which a program for timekeeping operations is written, a RAM in which data such as hours, minutes, seconds, etc. are stored, and an ALU that performs arithmetic processing, etc.
, a data bus that is connected to the RAM, ALU, etc. and transmits data; a display circuit that converts the data sent to the data bus into segment signals and stores them; and a display circuit that decodes instructions sequentially read from the ROM. a control circuit that outputs a signal to control each of the circuits; and a control circuit that outputs a signal that stops the operation of the clock generator based on the signal output from the control circuit, and that controls each of the plurality of switches. and a state control circuit that outputs a signal instructing detection of closing and opening of the plurality of switches, and a signal instructing whether or not to generate an interrupt signal when any of the plurality of switches is operated. The clock generator is characterized in that the input circuit restarts the operation of the clock generator in response to a signal that detects the closing or opening of a switch designated by the output of the state control circuit, or an interrupt signal generated by the operation of a switch. Electronic clock.