SU684494A1 - Device for synchronizing time-pieces by reference pulses from the source - Google Patents

Description

(54) DEVICE FOR SYNCHRONIZATION OF SUPPORT WATCH PULSES FROM THE SOURCE

I

The invention relates to the field of direct boring and can be used to improve the reliability and accuracy of clock synchronization.

Known clock synchronization systems

HF 1

With solenoid 1J.

However, these systems do not provide high accuracy of clock synchronization, due to the dependence on the parameters of the reference clock.

A device for synchronizing clocks is known, which contains a trigger regulator, a correction element, and an indicator of the current time 2.

This device, synchronization clock, provides high accuracy of clock synchronization of the system inertia.

The chain of the invention is to improve the accuracy of synchronization of clocks.

The goal is comprehended by the fact that the device also introduces a sensor for the phase of oscillations of the trigger controller, a pulse shaper, a n-bit shift register, logic gates AND NOT, a delay element, two logic gates OR, a key, a pulse generator, a frequency divider and an amplifier. The shaper, in this case, the sensor of the oscillation phase of the trigger controller is connected via a pulse shaper to the input of the first-bit installation of the n-bit Savig register to the state and to the installation's inputs to the state About of the other bits as well to one of the inputs of the logical element AND and the input of the first logical element OR, the other input of which is connected to the output of the n-th bit of the discharge shift register connected through the delay element and the logical element NOT to the second input of the logical element AND connected to the second logical the OR element, while the output of the first logical element OR is connected via a key to the control input of the pulse generator, the output of which popg the keys to the second input of the second logical element OR and the synchronization input of the MI. shift register, and the output of the second logical epemenga OR is connected to the input of the frequency divider, the reset bus of which is connected to the source of the reference pulses, and the output through the amplifier-shaper is connected to the current time indicator. The drawing shows a diagram of the device. The device contains an oscillation phase sensor of the trigger controller 1, the trigger controller 2, the pulse shaper 3, the h-bit shift register 4, the logic element AND 5, the logic element OR 6, the delay element 7, the logical element HE 8, the key 9 pulse generator 10, logic element OR 11, frequency divider 12, amplifier-driver 13 and current time indicator 14,, The device operates as follows. The oscillator of the trigger regulator 2 oscillates at a frequency f o. The sensor of the phase of oscillations of the trigger regulator 1 connected to it converts the phase of the mechanical oscillations of the oscillator into electric pulses corresponding to the moments of oscillator transition through the equilibrium position. The information about the phase of oscillations of the trigger regulator 2 as a sequence of electrical pulses is fed to the pulse formation circuit 3, which brings them in line with the requirements for electrical signals supplied to the inputs of the n-bit shift register 4 and the inputs of logic elements AND 5 and OR 6. In the proposed device, a shift register 4 is used, containing p-rads, designed to extract the signal controlling the starting and stopping of the pulse generator 10. The pulse-generator 1O reproduces the signal with the frequency f b, which is fed to the synchronization input of the n-bit shift register 4 and through the logic element OR 11 to the input of a frequency divider with a division factor of m 12. The frequency of the pulse generator 10 is determined from the formula r.

frequency of oscillation trigger

regulator 2,

number of bits of the register

n shift 4.

will be transferred to the 4th shift register 4 and will stop the pulse generator 10. Consequently, the pulse generator 10 is started by the trigger 2, and it is stopped by the pulse generator 10 with the start of the pulse generator 10, it is synchronized. Stopping occurs if the input of the key 9 is supplied from the output of the logical element OR 6. Since the inputs of the logical element OR, 6 1 can be received both from the output of the n-th digit of the shift register 4, and from the output of the pulse driver 3, then stop the pulse generator 10 is produced either by the shift register 4 or by the pulse shaper 3. The pulse generator 10 starts at the appearance of O on both inputs of the logic element OR 6. In the initial position, the information is distributed in the P-bit of the shift register 4 as follows: dah except for the Ts-th, O and in the nth digit of the shift register 4 is written 1. In this case, 1 at the output of the I-th bit of the shift register 4 through the logical element OR 6 and the key 9 stops the pulse generator 1O. The output of the pulse generator 3 is connected to the input S of the installation in the state i of the first bit of the c-bit shift register 4 and to the inputs R, Rgj ... of the setting to the state O of the other bits of the shift register 4. Thus, the pulse from the output pulse generator 3 leads to the redistribution of information in shift register 4, namely: it is written for the first bit, and O “.in all other bits of shift register 4. Zero at output | t of th digit and shift register 4 and end of pulse frequency generator 3 output corresponds to the generator start 1Opulses, and it starts to give pulses with a frequency i, which arrive at the synchronization input of the shift register 4 and the input C of the logic element OR 11. Information is transmitted in the discharge shift register 4 by pulses from the pulse generator 10 with the frequency | for the first discharge of the shift register 4 by the pulse from the output of pulse generator 3 through the time determined by the formula L --- r-C27,