JP3150833B2 - Logic circuit and electronic clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic timepiece having a logic speed-up / down circuit for adjusting the rate of an electronic timepiece,
And an electronic device with a logic circuit.

[0002]

2. Description of the Related Art Conventionally, a method has been used in which a circuit as shown in FIG. The operation will be briefly described based on FIG. 2 and FIG. 3 showing a timing chart.

The reference clock a output from the oscillation circuit 201 is a T-type flip-flop (hereinafter referred to as TFF) 20.
It is input to a frequency dividing circuit composed of 2 to 205 and divided. When the acceleration / deceleration operation is not performed, the frequency is accurately divided by よ う as in the section AB in FIG. When the acceleration / deceleration start command b rises at a certain timing, the acceleration / deceleration operation is started. Usually, the slow start command b rises every 10 seconds. The slow / fast start command b is input to the data of the latch circuit 208 that uses the non-inverting (hereinafter referred to as Q) output signal of the TFF 204 of the frequency dividing stage as a clock signal. Inversion of the latch circuit 208 (hereinafter Q
The output signal c falls in synchronization with the rise of the Q output signal of the TFF 204. The QX output signal c of the latch circuit 208 is input to the NOR circuit 209. NO
The R circuit 209 receives the reference clock a and the Q of the latch circuit 208.
An X output signal c and a Q output signal d of a D-type flip-flop (hereinafter referred to as DFF) 210 are input.

As can be seen from the timing chart of FIG.
When the Q output signal of the FF 204 rises, the level of the reference clock a is “L” and the Q output signal level of the DFF 210 is also “L”.
Rises in synchronization with the fall of the QX output signal c of the latch circuit 208.

The output e of the NOR circuit 209 and the speed data f
Outputs of the AND circuits 206 and 207 having g as an input are connected to preset inputs of the TFFs 202 and 203. When the level of the speed data f is “H” and the level of g is “L”, the output signal h of the AND circuit 206 is output.
Becomes "H", and the level of the output signal i of the AND circuit 207 remains "L". Therefore, TFF2
02 is preset and the Q output signal is forced to "H".

Next, when the reference clock a rises at the timing shown in FIG. 3D, the output e of the NOR circuit 209 falls. The data input is fixed to the “H” level, and the Q output signal d of the DFF 210 clocked by the output e of the NOR circuit 209 is synchronized with the fall of the output e of the NOR circuit 209 and thereafter until the DFF 210 is reset.
H ”. Therefore, the output e of the NOR circuit 209 is maintained.
Maintain the “L” level.

When the output e of the NOR circuit 209 becomes "L" level, the preset of the TFF 202 is released. Since the reference clock a is continuously input to the TFF 202, FIG.
At the timing of E, the Q output signal of the TFF 202 is subjected to normal 1/2 frequency division after the fall.

By this series of operations, one section of the "L" level of the Q output signal of the TFF 202, that is, one cycle of the reference clock a is omitted. TFF20
From the viewpoint of the fall timing of the Q output signal of No. 5,
What should have fallen at the timing of FIG. 3G has fallen at the timing of FIG. 3F. As a result, the reference clock signal a is slowed down in the forward direction by one period.

The above-described logic slowing or slowing method in the direction of delay or advance in one cycle of the reference clock is already known and put to practical use.

[0010]

However, in the conventional logic slow / fast circuit, only the slow / fast logic of the reference clock in one cycle unit is possible, so that the resolution of the rate adjustment is fine and a high-precision timepiece is required. It was unsuitable for adjusting the rate.

For example, a watch with an annual difference of 20 seconds (accuracy error throughout the year is within 20 seconds) has a rate standard of ± 32 msec /
d, for example, 262 kHz
Assuming that the crystal oscillation of z is used, the adjustment amount for one cycle of logical slowing / gaining is 32 msec / d. In consideration of the error of the rate measurement, etc., there has been a problem that it is very difficult to adjust the rate by varying logical speed data in mass production of high-precision timepieces.

When a high-precision clock is to be implemented with the conventional logic slow / fast circuit, the load itself in the oscillation circuit is periodically changed to finely adjust the frequency of the reference clock, thereby achieving a finer slow / fast resolution. There is a way to get
There has been a problem that a complicated control circuit and load capacity adjustment work are required.

[0013]

According to the present invention, in order to make the resolution finer and finer without the need for complicated control circuits and load capacity adjustment work, the present invention provides a slow / fast data input means for a half cycle of a reference clock. And data holding means,
By providing a half-period grading means that can decay in half-period units of the reference clock between the oscillating means and the frequency dividing means, a logic having a smaller grading resolution can be obtained without changing the grading range, in combination with the conventional one-period logic deciding means. Speed can be realized.

[0014]

According to the present invention, in order to realize the above function, the oscillating means 101 in FIG. 1 outputs a reference clock. The logical speed data input means 108 inputs speed data. The logical acceleration / deceleration data holding unit 107 receives and stores the output signal output from the logical acceleration / deceleration data input unit 108. The half-period logical acceleration / deceleration means 102 receives the output signal of the logical acceleration / deceleration data holding means 107 and performs logical acceleration / deceleration in units of a half cycle of the reference clock. The frequency dividing means 103 receives the clock output from the half-period logical accelerating / decreasing means 102 and divides the frequency. The one-period logical acceleration / deceleration means 106 receives the output signal of the logical acceleration / deceleration data holding means 107 and
02 is performed in one cycle unit of the clock output from the logic circuit. With the above configuration, the logic slowing / adjusting circuit of the present invention performs logic slowing / fastening in units of a half cycle of the reference clock.

In the electronic timepiece using the logic slowing / adjusting circuit of the present invention, the logic slowing / fastening in half-cycle units can be performed by adding a simple logic element, so that a highly accurate time display is possible.

[0016]

An embodiment of the present invention will be described with reference to the drawings.
FIG. 4 is a circuit diagram showing an example of the basic configuration of the embodiment of the logic moderator circuit of the present invention.

The crystal oscillation circuit 401 outputs a reference clock signal a. In this embodiment, the signal has a frequency of 262 kHz. The half-period logical acceleration / deceleration circuit 415 receives the reference clock signal a, the control signal k output from the frequency divider 416, the VCW control signal d output from the one-period logical acceleration / deceleration circuit 417, and the logical acceleration / deceleration data VCWD1, and receives the logical acceleration / deceleration data VC.
When WD1 is at the “H” level, the half cycle logic of the reference clock signal a is adjusted in synchronism with the control signal k output from the frequency dividing circuit 416, and the frequency-divided basic clock 1 serving as the input clock of the frequency dividing circuit 416 is output. I do. This half cycle logic 415
Are exclusive OR (hereinafter referred to as EXOR) circuit 402, latch circuit 409, AND circuit 410, and TFF
411. The detailed operation will be described later.

The frequency dividing circuit 416 includes TFFs 403 to 406.
It consists of. Actually, a control signal for operating the display drive circuit must be output.
Are connected to several stages of TFFs, but are omitted here. The one-period logical slowing / advancing circuit 417
2, NOR circuit 413, DFF 414, and AND circuit 40
7, 408. The one-cycle logic regulation circuit 417 is
The divided basic clock 1 output from the half-period logical acceleration / deceleration circuit 415, the acceleration / deceleration operation start signal VCWDR, the control signal j output from the frequency divider 416, the logical acceleration / deceleration data VCWD2, VCW
D3 is input, and the logic speed data VCWD2, VCWD
3 is synchronized with the control signal j output from the frequency dividing circuit 416 when one or both of them are at the “H” level.
1 cycle logical slow / fast operation signals m and n for presetting each of the TFFs. The detailed operation has already been described in the section of the prior art, so that the description is omitted.

In the configuration of this embodiment, the slow / fast operation start signal V
When the CWDR rises, a one-cycle logic operation is performed at the next fall of 64 kHz, and a half-cycle logic operation is performed at the next fall of 64 kHz. FIG. 5 is a timing chart of the present embodiment.

The half-period logical slowing operation including the one-period logical slowing operation will be described in detail. Velocity operation start signal VCWDR
Rises (5-A), as described in the section of the prior art, a one-cycle logical slow / fast operation signal is output from the NOR circuit 413 in synchronization with the next fall of 64 kHz (5-A).
B). It has already been described that the control signal d when this one-cycle logic slow / fast operation signal falls is the Q output signal of the DFF 414. Further, the control signal d is obtained by comparing the data of the latch circuit 409 in the half-period logical acceleration / deceleration circuit 415 with the AND circuit 4
10 is input.

The AND circuit 410 has three inputs.
One of the inputs is half-period logical acceleration / deceleration data VCWD1.
Here, it is assumed that "H" level is maintained as data for performing half-cycle logic slowdown. The other input of the AND circuit 410 receives the QX output signal of the latch circuit 409.

The latch circuit 409 receives the Q output signal d of the DFF 414 in the one-period logic circuit 417 as a data input, and outputs the Q output signal k of the TFF 406 in the frequency dividing circuit 416.
(Here, a 16 kHz signal) is used as a clock signal. The QX output signal of the latch circuit 409 normally maintains the “H” level, and is synchronized with the rise of the next 16 kHz (signal k) after the rise of the Q output signal d of the DFF 414.
It falls to the L "level (5? D).

The output of the AND circuit 410 to which the Q output signal d of the DFF 414, the half-period logic slow / fast data VCWD1, and the QX output signal of the latch circuit 409 are input is the DFF 414.
Rises in synchronization with the rise of the Q output signal d (5)
-C). Here, the half cycle logical speed data VCWD1 is "
In the case of L level, one of the inputs of the AND circuit 410 is “
The output of the AND circuit 410 becomes DFF
The "L" level is maintained irrespective of the change in the Q output signal d at 414, and therefore, the half-cycle logical operation is not performed.

The half cycle logical speed data VCWD1 is "H".
If the output of the AND circuit 410 becomes “H” level, the QX output signal of the latch circuit 409 becomes TFF4
06 falls in synchronization with the rise of the Q output signal k ( 16 kHz in this case). At the same time, the output of the AND circuit 410 that receives the QX output signal of the latch circuit 409 also falls (5? E). The output signal of the AND circuit 410 is input to the clock of the TFF 411 in the falling operation, so that the Q output signal o of the TFF 411 is inverted (5?
F). The Q output signal o of the TFF 411 is
2 is input.

The other input of the EXOR circuit 402 is a reference clock signal a which is an output signal of the oscillation circuit 401.
The frequency dividing circuit 41 including the operation of the EXOR circuit 402 in FIG.
6 shows a timing chart of the output signal of each TFF.
In FIG. 6, the upper part shows a state in which the half-period logical acceleration / deceleration operation is not performed, and the lower part shows that the half-period logical acceleration / deceleration operation is (6-A).
The state at the time of performing is shown.

The Q output signal o of the TFF 411 is (6-A)
, The output signal 1 of the EXOR circuit 402 changes from “L” level to “H” level. That is, the period of the reference clock signal a at the “L” level is omitted, and the reference clock signal “a” is forced to the “H” level.

Thereafter, the output signal 1 of the EXOR circuit 402
Keeps outputting the inverted clock of the output of the oscillation circuit 401 as the other input signal until the Q output signal o of the TFF 411 is inverted. The output signal 1 of the EXOR circuit 402 is used as the frequency division basic clock 1 of the frequency division circuit 416 as the frequency division circuit 416.
After that, the frequency is divided. Each TF of the frequency divider 416
Looking at the Q output signal of F in the timing chart of FIG.
The Q output signal of the TFF 403 rises a half cycle of the reference clock signal a earlier than a normal rise (6-
B), the Q output signal of the TFF 404 rises earlier by a half cycle of the reference clock signal a than usual (6-C).

Similarly, the output signal of each TFF thereafter changes earlier by a half cycle of the reference clock signal a.
Can be realized in units of a half cycle. In the embodiment of the present invention, a display drive circuit for inputting an output signal of the frequency dividing means 416 and outputting a drive signal for driving a display element, and a display drive output signal for outputting a display drive output signal of the display drive circuit and receiving time information. And so on, an electronic timepiece having a logical speed-up / down circuit can be realized. An electronic timepiece having this logical speed-up / down circuit can be of very high precision.

As the display element, a motor and a pointer or a liquid crystal panel or the like is preferably used. Further, by applying the logic regulation circuit of the present invention, it is possible to realize an electronic device with a logic regulation circuit that displays and reports time information such as a highly accurate timer, stopwatch, and alarm device.

[0030]

As described above, according to the present invention, the oscillating means for outputting the reference clock, the logical speed data input means for inputting speed data, and the output signal of the logic speed data input means are input and stored. Logic slow / fast data holding means, a half cycle logic slow / fast means for inputting an output signal of the logic slow / fast data holding means and performing logic slow / fast in half cycle of the reference clock, and a signal output from the half cycle logic slow / fast means. Frequency dividing means, and a one-period logical acceleration / deceleration means for inputting an output signal of the logical acceleration / deceleration data holding means and performing a logical acceleration / deceleration in one cycle unit of a clock output from the half-period logical acceleration / deceleration means. Accordingly, there is an effect that the logic can be adjusted with high accuracy in a half cycle of the reference clock with a simple element configuration.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an example of a basic configuration of an electronic timepiece with a logic speed-up / down circuit according to the present invention.

FIG. 2 is a circuit diagram of a conventional logic regulation circuit.

FIG. 3 is a timing chart of a slow / fast operation of a conventional logic slow / fast circuit.

FIG. 4 is a circuit diagram of an embodiment of a logic moderator circuit of the present invention.

FIG. 5 is a timing chart of an embodiment of the logic moderator circuit of the present invention.

FIG. 6 is a timing chart of a half-period regulation section of the embodiment of the logic regulation circuit of the present invention.

[Explanation of symbols]

 Reference Signs List 101 oscillation means 102 half-period logical slow / fast means 103 frequency dividing means 104 waveform shaping means 105 display means 106 one-period logical slow / fast means 107 logical slow / fast data holding means 108 logical slow / fast data input means

Claims (4)

(57) [Claims] An oscillator for outputting a reference clock;
1) and a logical speed data input means (10) for inputting speed data.
8), a half-period logical acceleration / deceleration means (102) for inputting an output signal of the logical acceleration / deceleration data input means (108) and performing logical acceleration / deceleration in units of a half cycle of the reference clock, and an output of the half-period logical acceleration / deceleration means (102) Frequency dividing means (103) for inputting a clock to be divided and dividing the frequency, and inputting the output signal of the logical slow / fast data input means (108) and outputting a logical signal in one cycle unit of the clock output from the half-period logical slow / fast means (102) One-cycle logic acceleration / deceleration means (10
6) a logic slowing / fastening circuit. 2. An oscillating means (10) for outputting a reference clock.
1) and a logical speed data input means (10) for inputting speed data.
8), a half-period logical acceleration / deceleration means (102) for inputting an output signal of the logical acceleration / deceleration data input means (108) and performing logical acceleration / deceleration in units of a half cycle of the reference clock, and an output of the half-period logical acceleration / deceleration means (102) Frequency dividing means (103) for inputting a clock to be divided and dividing the frequency, and inputting the output signal of the logical slow / fast data input means (108) and outputting a logical signal in one cycle unit of the clock output from the half-period logical slow / fast means (102) One-cycle logic acceleration / deceleration means (10
6) and the output signal of the frequency dividing means (103) are input to display means (1).
A display driving means (104) for outputting a driving signal for driving the display driving means (05), a display means (105) for receiving a display driving output signal output from the display driving means (104) and displaying time information and the like; An electronic timepiece comprising: 3. A logic speed data input means (108) for inputting speed data, and a logic speed data input means (10).
8) A predetermined period logic slowing / decreasing means (10) which receives the output signal of 8) and performs logic slowing / decreasing in a predetermined cycle unit shorter than the reference clock.
2) and frequency changing means (10) for inputting an output signal output from the logic means for predetermined period (102) to change the frequency.
3), and a periodic logical acceleration / deceleration means (106) for receiving an output signal of the logical acceleration / deceleration data input means (108) and performing a logical acceleration / deceleration based on an output signal output from the logical periodicity data of the predetermined period (102).
And a logic moderator circuit having: 4. A display driving means (104) for outputting a driving signal for driving a display means (105) based on an output signal output from a frequency changing means (103) of the logic slowing / fastening circuit according to claim 3. And a display means (105) for receiving a display drive output signal output from the display drive means (104) and displaying timekeeping information.